FDC37C665GT Standard Microsystems (SMSC), FDC37C665GT Datasheet - Page 38

• Manufacturer Part Number: FDC37C665GT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT

• Lead Free Status / RoHS Status: Not Compliant

CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no
functionality. It can be read by bit 2 of the DSR
when in Model 30 register mode. Unaffected by
software reset.
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 16 shows the state of the DENSEL pin.
The DENSEL pin is set high after a hardware
reset and is unaffected by the DOR and the
DSR resets.
RESET
COND.
RESET
COND.
See Table 13 for the appropriate
See Table 13 for the appropriate
N/A
N/A
7
7
N/A
N/A
6
6
N/A
N/A
5
5
N/A
38
N/A
4
4
BIT 2 - 7 RESERVED
Should be set to a logical "0"
N/A
N/A
3
3
Data Rate
500kbps
250kbps
Table 16 - DENSEL Encoding
300kps
1Mbps
NOPREC DRATE
N/A
N/A
2
2
DRATE
SEL1
IDENT
SEL1
1
1
1
1
0
1
0
1
0
1
0
1
DRATE
DRATE
SEL0
SEL0
DENSEL
0
0
0
0
0
1
0
1
1
0
1
0