UPD720122F1-DN2-A Renesas Electronics America, UPD720122F1-DN2-A Datasheet - Page 23

• Manufacturer Part Number: UPD720122F1-DN2-A
• Manufacturer: Renesas Electronics America

Specifications of UPD720122F1-DN2-A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.6.2
(1) CPU BUS read operation
CPU bus read timing
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Symbol
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
A7 to A1
CSB
RDB
WRB
D15 to D0
AC characteristics of BIU block with Function 1 selected
Read cycle time
Address setup time (RDB↓)
Chip select setup time (RDB↓)
Buffer direction change time (RDB↓)
Output data delay time (RDB↓)
Read command width
Chip select hold time (RDB↑)
Address hold time (RDB↑)
RDB inactive time
Output data hold time (RDB↑)
High level
t
t
2
3
t
4
Parameter
INVALID
t
5
Data Sheet S16685EJ3V0DS
VALID
t
6
t
1
VALID
t
Min.
10
91
57
34
5
5
−
−
5
5
4
t
t
8
7
Typ.
High level
t
9
µ
PD720122
Max.
14
57
∞
∞
∞
∞
∞
∞
∞
−
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21