UPD720122F1-DN2-A Renesas Electronics America, UPD720122F1-DN2-A Datasheet - Page 32

• Manufacturer Part Number: UPD720122F1-DN2-A
• Manufacturer: Renesas Electronics America

Specifications of UPD720122F1-DN2-A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

(c) CPU bus DMA demand read transfer timing
(Overall)
30
T45
T46
T47
T48
T49
T50
T51
T52
T53
T54
T55
T56
T57
T69
T71
T72
T74
Symbol
EP1_DACKB
EP1_DRQB
RDB
D15 to D0
EP1_TCB
EP1_STOPB
Note
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
Can be input after immediately previous RDB ↑ .
DMA request acknowledge setup time (RDB ↓ )
DMA demand mode read transfer cycle time
Read command width
Read command inactive time
Read data delay time (RDB ↓ )
Buffer direction change time (RDB ↓ )
Read data hold time (RDB ↑ )
EP1_TCB setup time (RDB ↓ )
EP1_TCB hold time (RDB ↓ )
EP1_STOPB delay time (RDB ↓ )
EP1_STOPB delay time (RDB ↑ )
DMA request off time (RDB ↑ )
DMA request acknowledge hold time (RDB ↑ )
DMA request off time (EP1_DACKB ↓ )
DMA request off time (EP1_DACKB ↓ ) 1 cycle transfer
DMA request on time (EP1_DACKB ↑ )
DMA request off time (RDB ↓ )
High level
High level
t
45
t
50
t
49
t
47
1 cycle
t
46
t
48
t
51
Parameter
Data Sheet S16685EJ3V0DS
Min.
91
57
34
17
0
−
−
4
0
−
3
−
0
−
−
−
−
N − 1 cycle
Typ.
t
56
EP1_STOPB is not asserted in the
case of a full packet.
t
54
µ
Note
PD720122
Max.
57
14
15
59
38
38
88
60
∞
∞
∞
∞
∞
∞
−
−
N cycle
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
t
57