UPD720122F1-DN2-A Renesas Electronics America, UPD720122F1-DN2-A Datasheet - Page 72

• Manufacturer Part Number: UPD720122F1-DN2-A
• Manufacturer: Renesas Electronics America

Specifications of UPD720122F1-DN2-A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

70
(3) USB connection sequence on USB1.1 bus
USB bus
USBRST
SPMODE
The PHY core implemented on the
Check the SP_MODE bit (SP_MODE) of the Int Status 2 register after an EPC2_STG bus reset interrupt has
occurred to determine whether the USB is connected to FS or HS.
Differential
data lines
T
PERIOD
Pull-up is active.
FS J
High
T
0
Figure 2-11. USB Receiver Jitter Tolerance for Full-Speed
Figure 2-12. USB Connection Sequence on USB 1.1 Bus
t
HDS
N * T
µ
T
PD720122 automatically determines the Up port.
xJR
Consecutive
transitions
PERIOD
t
FCA
Data Sheet S16685EJ3V0DS
+ T
t
SCA
xJR1
N * T
Chirp K device out
transitions
PERIOD
Paired
t
CKO
t
t
CKI
DRS
+ T
xJR2
T
xJR1
t
SCS
Reversion to full-speed mode
µ
PD720122
T
xJR2
FS J