UPD720122F1-DN2-A Renesas Electronics America, UPD720122F1-DN2-A Datasheet - Page 36

• Manufacturer Part Number: UPD720122F1-DN2-A
• Manufacturer: Renesas Electronics America

Specifications of UPD720122F1-DN2-A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

(d) CPU bus DMA demand write transfer timing
(Overall)
34
T58
T59
T60
T61
T62
T63
T64
T65
T66
T67
T70
T73
T75
Symbol
Note
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
EP2_DRQB
EP2_DACKB
WRB
D15 to D0
EP2_TCB
Can be input after immediately previous WRB ↑ .
DMA request acknowledge setup time (WRB↓)
DMA demand mode write transfer cycle time
Write command width
Write command inactive time
Write data setup time (WRB↑)
Write data hold time (WRB↑)
EP2_TCB setup time (WRB↓)
EP2_TCB hold time (WRB↓)
DMA request off time (WRB↑)
DMA request acknowledge hold time (WRB↑)
DMA request off time (EP2_DACKB↓)
DMA request on time (EP2_DACKB↑)
DMA request off time (WRB↓)
High level
t
58
t
60
t
1 cycle
62
t
59
t
63
t
61
Parameter
Data Sheet S16685EJ3V0DS
Min.
72
38
34
10
17
0
0
0
−
0
−
−
−
N − 1 cycle
Typ.
t
66
µ
Note
PD720122
Max.
60
38
88
60
∞
∞
∞
∞
∞
∞
∞
∞
t
N cycle
67
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns