CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 16

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect either an external oscillator or a crystal
to these pins. A 6-MHz fundamental crystal can be connected to these pins to provide a reference frequency for the internal PLL.
A ceramic resonator will not allow the microcontroller to meet the timing specifications of a high speed USB and therefore a
ceramic resonator is not recommended with these parts.
An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Please note that grounding the
XTALOUT pin when driving XTALIN with an oscillator will not work as the internal clock is effectively shorted to ground.
7.0
The CY7C66xxx supports two resets: Power-On Reset (POR) and a Watch Dog Reset (WDR). Each of these resets will cause:
The occurrence of a reset is recorded in the Processor Status and Control Register located at I/O address 0xFF. Bits 4 and 6 are
used to record the occurrence of POR and WDR respectively. Firmware can interrogate these bits to determine the cause of a
reset.
Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware
reset handler should configure the hardware before the “main” loop of code. Attempting to execute either a RET or RETI in the
firmware reset handler will cause unpredictable execution results.
7.1
The CY7C66xxx enters a suspend state when the V
during this suspend time and ensures that both a valid V
When the V
The first 1 ms of suspend time is not interruptible, but the suspend state will continue for an additional 127 ms unless the count
is bypassed by a USB Bus Reset interrupt on the upstream port. Upon a USB Bus Reset, the interrupt will be pending and the
IRQ is generated only after the firmware enables the Interrupt Mask (bit 2 of register 0xFF) and the USB Bus Reset interrupt (b it
0 of register 0x20). This 127 ms time period guarantees that when the V
voltage the chip will not execute code. If the oscillator is stable and V
127 ms of suspend to be bypassed. When 127 ms has passed or a USB Bus Reset is asserted, the chip will immediately begin
execution of code at address zero (0x0). Notice that this response to a USB Bus Reset will only occur after a minimum of 1 ms
to allow the PLL to stabilize.
The POR signal will also be asserted if V
V
7.2
The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 4-bit Watch Dog Timer Register (0x26)
transitions from LOW to HIGH. In addition to the normal reset initialization noted under “Reset”, bit 6 of the Processor Status and
Control Register is set to ‘1’ to indicate to the firmware that a Watch Dog Reset occurred.
The Watch Dog Timer is clocked by a 1.024-ms clock (bit 9) from the free-running timer. The 1.024-ms clock is the same timer
output that can be used to interrupt the processor every 1.024 ms. Writing any value to the write-only Watch Dog Clear I/O regi ster
(0x26) will clear the 4-bit Watch Dog Timer.
• all Registers to be restored to their default states,
• the USB Device Addresses to be set to 0,
• all interrupts to be disabled,
• the Program Stack Pointer (PSP) and Data Stack Pointer (DSP) to be set to memory address 0x00.
CC
value once again rises above V
Power-On Reset (POR)
Watch Dog Reset (WDR)
Reset
CC
has risen above V
Last write to
Watch Dog Timer
Register
rst
and the oscillator is stable the POR is deasserted and the on-chip timer will start counting.
rst
. Behavior is the same as described above.
PRELIMINARY
CC
drops below the predetermined value (V
Figure 7-1. Watch Dog Reset (WDR)
t
WATCH
No write to WDT
register, so WDR
goes HIGH
CC
is first applied to the chip. The Power-On Reset (POR) signal is asserted
CC
level (V
16
2 ms
rst
CC
) is reached and that the internal PLL has time to stabilize.
is above V
CC
Execution begins at
Reset Vector 0X00
ramp takes a very long time to reach full operating
rst
, a USB Bus Reset will cause the additional
rst
). The POR will remain asserted until the
CY7C66011/12/13
CY7C66111/12/13