CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 24

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

The “USB Bus Reset Interrupt” (bit 5) will occur when a USB Bus Reset is received. The USB Bus Reset is a singled-ended zero
(SE0) that lasts at least 12–16 s. An SE0 is defined as the condition in which both the D+ line and the D– line are LOW at the
same time. When the SIE detects this condition, the USB Bus Reset interrupt bit is set in the Processor Status and Control register
and an USB Bus Reset interrupt is generated.
The “Watch Dog Reset” (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went
for more than t
The “IRQ pending” (bit 7) indicates one or more of the interrupts has been recognized as active. The interrupt acknowledge
sequence will clear this bit until the next interrupt is detected.
During Power-On Reset, the Processor Status and Control Register is set to 00010001, which indicates a Power-On Reset (bit
4 set) has occurred and no interrupts are pending (bit 7 clear).
During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watch Dog Reset
(bit 4 set) has occurred and no interrupts are pending (bit 7 clear).
15.0
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a
‘1’ to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable
Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts.
Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the
hardware will first disable all interrupts by clearing the Interrupt Mask bit in the Processor Status and Control Register. Next, the
interrupt latch of the current interrupt is cleared. This is followed by a CALL instruction to the ROM address associated with the
interrupt being serviced (i.e., the Interrupt Vector). The instruction in the interrupt table is typically a JMP instruction to the address
of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI
instruction. Interrupts can be nested to a level limited only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are automatically stored onto the Program Stack by the
CALL instruction as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the processor
state is preserved and restored during an interrupt. The PUSH A instruction should be used as the first command in the ISR to
save the accumulator value and the POP A instruction should be used just before the RETI instruction to restore the accumulator
value. The program counter, CF, and ZF are restored and interrupts are enabled when the RETI instruction is executed.
15.1
The Interrupt Vectors supported by the USB Controller are listed in Table 15-1 . The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I
an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds to the first entry in t he
Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.
Reserved
Reserved
7
0
7
0
Interrupt Vectors
Interrupts
WATCH
Reserved
Interrupt
Enable
(8 ms minimum) between Watch Dog clears.
R/W
I
2
6
6
0
C
Figure 15-2. USB Endpoint Interrupt Enable Register 0x21 (read/write)
Figure 15-1. Global Interrupt Enable Register 0x20 (read/write)
GPIO/HAPI
Reserved
Interrupt
Enable
R/W
5
5
0
PRELIMINARY
Interrupt
Interrupt
Enable
Enable
EPB1
DAC
R/W
R/W
4
4
24
USB Hub
Interrupt
Interrupt
Enable
Enable
EPB0
R/W
R/W
2
3
3
C interrupt) has the lowest priority. Although Reset is not
1.024-ms
Interrupt
Interrupt
Enable
Enable
EPA2
R/W
R/W
2
2
CY7C66011/12/13
CY7C66111/12/13
Interrupt
Interrupt
128- s
Enable
Enable
EPA1
R/W
R/W
1
1
USB Bus RST
Interrupt
Interrupt
Enable
Enable
EPA0
R/W
R/W
0
0