CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 10

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

The Cortex-M3 CPU subsystem includes these features:
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4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
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Document Number: 001-55034 Rev. *G
ARM Cortex-M3 CPU
Programmable nested vectored interrupt controller (NVIC),
tightly integrated with the CPU core
Full-featured debug and trace modules, tightly integrated with
the CPU core
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
Cache controller
Peripheral HUB (PHUB)
DMA controller
External memory interface (EMIF)
4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
The Thumb
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
SRAM
SRAM
32 KB
32 KB
®
Interrupt Inputs
-2 instruction set, which offers ARM-level
JTAG/SWD
Bus
Matrix
Bus
Matrix
Debug Block
AHB Spokes
(Serial and
Controller
Vectored
Interrupt
Nested
(NVIC)
JTAG)
GPIO &
EMIF
AHB
I- Bus
Figure 4-1. ARM Cortex-M3 Block Diagram
AHB Bridge & Bus Matrix
PRELIMINARY
C-Bus
D-Bus
AHB
Digital
Prog.
Cortex M3 CPU Core
Peripherals
PHUB
AHB
S-Bus
Cortex M3 Wrapper
Analog
Prog.
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4.1.2 Cortex-M3 Operating Modes
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
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The Cortex-M3 does not support ARM instructions.
Bit-band support. Atomic bit-level write and read operations.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
Extensive interrupt and system exception support.
PSoC
Bit-field control
Hardware multiply and divide
Saturation
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
DMA
Bus
Matrix
Functions
Special
®
Watchpoint and
Instrumentation
and Breakpoint
Trace Module
Trace (DWT)
Flash Patch
5: CY8C52 Family Datasheet
(FPB)
(ITM)
Data
Cache
Trace Module
Interface Unit
Embedded
Trace Port
(TPIU)
(ETM)
256 KB
Flash
ECC
Trace Pins:
5 for TRACEPORT or
1 for SWV mode
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