CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 9

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

3. Pin Descriptions
IDAC0. Low resistance output pin for high IDAC.
Extref0, Extref1. External reference input to the analog system.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense
I2C0: SCL, I2C1: SCL. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33-MHz crystal oscillator
pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK. Serial wire debug clock programming and debug port
connection.
SWDIO. Serial wire debug Input and output programming and
debug port connection.
TCK. JTAG test clock programming and debug port connection.
TDI. JTAG test data In programming and debug port connection.
TDO. JTAG test data out programming and debug port
connection.
TMS. JTAG test mode select programming and debug port
connection.
TRACECLK. Cortex-M3
TRACEDATA pins.
TRACEDATA[3:0]. Cortex-M3
output data.
SWV. Single wire viewer output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
Document Number: 001-55034 Rev. *G
Notes
7. GPIOs with opamp outputs are not recommended for use with CapSense.
8. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
[7]
.
2
2
C SCL line providing wake from sleep
C SDA line providing wake from sleep
TRACEPORT
TRACEPORT
connection,
PRELIMINARY
connections,
DDD
2
2
C SDA if
C SCL if
instead
clocks
of from a V
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
USB.
V
V
V
Requires a 1 µF capacitor to V
external use.
V
The two V
between them as short as possible, and a 1-µF capacitor to
V
external use.
V
regulator. V
device. All other supply pins must be less than or equal to V
V
V
V
V
V
V
V
and must be less than or equal to V
with V
should be tied to ground (V
XRES (and configurable XRES). External reset pin. Active low
with internal pull-up. In 48-pin SSOP parts, P1[2] is configured
as XRES. In all other parts the pin is configured as a GPIO.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C52 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
BOOST
BAT
CCA
CCD
SSD
DDA
DDD
DDD
SSA
SSB
SSD
DDIO0
DDIO
PSoC
. Battery supply to boost pump.
; see
. Ground for all analog peripherals.
. Ground connection for boost pump.
. Ground for all digital logic and I/O pins.
[8]
[8]
. Output of analog core regulator and input to analog core.
. Output of digital core regulator and input to digital core.
. Supply for all analog peripherals and analog core
. Supply for all digital peripherals and digital core regulator.
must be less than or equal to V
DDIO0
must be tied to a valid operating voltage (1.71 V to 5.5 V),
, V
. Power sense connection to boost pump.
DDIO1
CCD
Power System
DDIO
DDIO
DDA
, V
®
DDIO2
, V
5: CY8C52 Family Datasheet
. Pins are No Connect (NC) on devices without
. Pins are No Connect (NC) on devices without
pins must be shorted together, with the trace
must be the highest voltage present on the
DDIO2
or V
, V
DDIO3
on page 20. Regulator output not for
DDIO3
SSD
or V
. Supply for I/O pins. Each
are not used then that V
SSA
DDA
SSA
. Regulator output not for
DDA
. If the I/O pins associated
).
.
DDD
Page 9 of 85
instead
DDIO
DDA
[+] Feedback
.