CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet - Page 40

• Manufacturer Part Number: CY8C5246AXI-038
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-038

• Lead Free Status / RoHS Status: Compliant

7.7 Timers, Counters, and PWMs
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows designers to choose the timer, counter, and
PWM features that they require. The tool set utilizes the most
optimal resources available.
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
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Figure 7-21. Timer/Counter/PWM
7.8 I
The I
designed to interface the PSoC device with a two wire I
communication bus. The bus is compliant with Philips ‘The I
Specification’ version 2.1. Additional I
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
Document Number: 001-55034 Rev. *G
Clock
Reset
Enable
Capture
Kill
16-bit timer/counter/PWM (down count only)
Selectable clock source
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Timer capture mode
Count while enable signal is asserted mode
Free run mode
One Shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
2
2
C peripheral provides a synchronous two wire interface
C
Timer / Counter /
PWM 16-bit
2
C interfaces can be
IRQ
TC / Compare!
Compare
PRELIMINARY
2
C serial
2
C
To eliminate the need for excessive CPU intervention and
overhead, I
and generation of framing bits. I
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I
DSI routing and allows direct connections to any GPIO or SIO
pins.
I
CPU intervention. Additionally the device can wake from low
power modes on a 7-bit hardware address match. If wakeup
functionality is required, I
two special sets of SIO pins.
I
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8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
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2
2
C provides hardware address detect of a 7-bit address without
C features include:
Slave and master, transmitter, and receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low power modes on address match
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
Successive approximation (SAR) ADC
One 8-bit DAC that provides either voltage or current output
Two comparators with optional connection to configurable LUT
outputs
CapSense subsystem to enable capacitive touch sensing
Precision reference for generating an accurate analog voltage
for internal analog blocks
PSoC
2
C specific support is provided for status detection
®
5: CY8C52 Family Datasheet
2
C pin connections are limited to the
2
C operates as a slave, a master,
2
C interfaces through the
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