MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 123

• Manufacturer Part Number: MC9S08QD2CSC
• Manufacturer: Freescale

Specifications of MC9S08QD2CSC

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 4
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Program Memory Type: Flash
• Program Memory Size: 2KB
• Lead Free Status / RoHS Status: Compliant

9.1.2
Key features of the ICS module are:
9.1.3
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
9.1.3.1
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
9.1.3.2
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock. The BDC clock is supplied from the FLL.
9.1.3.3
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
9.1.3.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
Freescale Semiconductor
•
•
•
•
•
•
•
Frequency-locked loop (FLL) is trimmable for accuracy
— 0.2% resolution using internal 32 kHz reference
— 2% deviation over voltage and temperature using internal 32 kHz reference
Internal or external reference clocks up to 5 MHz can be used to control the FLL
— 3 bit select for reference divider is provided
Internal reference clock has 9 trim bits available
Internal or external reference clocks can be selected as the clock source for the MCU
Whichever clock is selected as the source can be divided down
— 2 bit select for clock divider is provided
Control signals for a low power oscillator as the external reference clock are provided
— HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
FLL engaged internal mode is automatically selected out of reset
– Allowable dividers are: 1, 2, 4, 8
– BDC clock is provided as a constant divide by 2 of the DCO output
Features
Modes of Operation
FLL Engaged Interna
FLL Engaged External
FLL Bypassed Interna
FLL Bypassed Interna
MC9S08QD4 Series MCU Data Sheet, Rev. 6
l (FEI)
l (FBI)
l Low Power (FBILP)
(FEE)
Internal Clock Source (S08ICSV1)
123