MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 35
MC9S08QD2CSC
Manufacturer Part Number
MC9S08QD2CSC
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QD2CSC.pdf
(198 pages)
Specifications of MC9S08QD2CSC
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
4
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
4-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Program Memory Type
Flash
Program Memory Size
2KB
Lead Free Status / RoHS Status
Compliant
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0x1800
0x1801
0x1802
0x1803
0x1804
0x1805
0x1806
0x1807
0x1808
0x1809
0x180A
0x180B–
0x181F
0x1820
0x1821
0x1822
0x1823
0x1824
0x1825
0x1826
0x1827–
0x183F
0x1840
0x1841
0x1842
0x1843–
0x1847
Nonvolatile flash registers, shown in
an 8-byte backdoor key that optionally can be used to gain access to secure memory resources. During
reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the flash memory
are transferred into corresponding FPROT and FOPT working registers in the high-page registers to
control security and block protection options.
Freescale Semiconductor
Address
This reserved bit must always be written to 0.
SRS
SBDFR
SOPT1
SOPT2
Reserved
Reserved
SDIDH
SDIDL
SRTISC
SPMSC1
SPMSC2
Reserved
FCDIV
FOPT
Reserved
FCNFG
FPROT
FSTAT
FCMD
Reserved
PTAPE
PTASE
PTADS
Reserved
Register Name
COPCLKS
KEYEN
FCBEF
DIVLD
COPE
LVWF
REV3
LVDF
RTIF
Bit 7
POR
ID7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
Table 4-3. High-Page Register Summary
MC9S08QD4 Series MCU Data Sheet, Rev. 6
LVWACK
FNORED
LVDACK
RTIACK
PRDIV8
COPT
Table
REV2
FCCF
PIN
ID6
—
—
—
—
—
—
—
—
—
6
0
0
0
0
0
0
4-4, are located in the flash memory. These registers include
RTICLKS
KEYACC
PTADS5
PTAPE5
PTASE5
FPVIOL
STOPE
LVDIE
REV1
LVDV
COP
ID5
—
—
—
—
—
—
—
—
—
5
0
0
0
FACCERR
PTAPE4
PTASE4
PTADS4
LVDRE
LVWV
REV0
ILOP
RTIE
FPS
ID4
—
—
—
—
—
—
—
—
—
4
0
0
0
0
0
FCMD
PTADS3
PTAPE3
PTASE3
LVDSE
PPDF
Chapter 4 Memory Map and Register Definition
ILAD
ID11
ID3
—
—
—
—
—
—
—
—
—
3
0
0
0
0
0
0
0
DIV
PPDACK
FBLANK
PTAPE2
PTASE2
PTADS2
LVDE
ID10
ID2
—
—
—
—
—
—
—
—
—
2
0
0
0
0
0
0
BKGDPE
PTAPE1
PTASE1
PTADS1
SEC01
RTIS
LVD
ID9
ID1
—
—
0
—
—
—
—
—
—
—
—
1
0
0
0
0
1
PTADS0
PTAPE0
PTASE0
RSTPE
SEC00
FPDIS
BDFR
BGBE
PPDC
Bit 0
ID8
ID0
—
—
—
—
—
—
—
—
—
0
0
0
0
35
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