A80960HD80S L2GK Intel, A80960HD80S L2GK Datasheet - Page 44

• Manufacturer Part Number: A80960HD80S L2GK
• Manufacturer: Intel

Specifications of A80960HD80S L2GK

• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 80MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Compliant

80960HA/HD/HT
44
Table 24. A.C. Characteristics Notes
Table 25. 80960Hx Boundary Scan Test Signal Timings
NOTES:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
† Not tested.
10.Relative Output timings are not tested.
12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for
11. Not tested.
1. See
2. See
3. See
4. Where N is the number of N
5. N = Number of wait states inserted with READY.
6. These specifications are ensured by the processor.
7. These specifications must be met by the system for proper operation of the processor.
8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However,
9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times
BSF
BSC
BSCH
BSCL
BSCR
BSCF
BSIS1
BSIH1
BSOV1
BSOF1
BSOV2
BSOF2
BSIS2
BSIH2
Symbol
for output delays and hold times.
derating information for rise and fall times.
Controller Region Table. WAIT never goes active when there are no wait states in an access.
to ensure the device exits the reset mode synchronized to a particular clock edge, the rising edge of
RESET must meet setup and hold times to the rising edge of the CLKIN.
for proper operation. These pins are sampled by the interrupt controller every clock and must be active for
at least two consecutive CLKIN rising edges when asserting them asynchronously. To ensure recognition at
a particular clock edge, the setup and hold times shown must be met.
the following signals: A31:4, SUP, CT3:0, D/C, LOCK, W/R, BE3:0.
Figure 25, “Output Delay or Hold vs. Load Capacitance” on page 52
Section 4.8, “AC Timing Waveforms” on page 46
Figure 22, “Rise and Fall Time Derating at 85 °C and Minimum VCC” on page 51
TCK Frequency
TCK Period
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
Input Setup to TCK —
TDI, TMS
Input Hold from TCK —
TDI, TMS
TDO Valid Delay
TDO Float Delay
All Outputs (Non-Test)
Valid Delay
All Outputs (Non-Test)
Float Delay
Input Setup to TCK - All
Inputs (Non-Test)
Input Hold from TCK - All
Inputs (Non-Test)
Parameter
RAD
, N
RDD
, N
Min
125
WAD
40
40
10
10
0
8
3
3
8
or N
Infinite
WDD
Max
30
36
30
36
8
8
8
for waveforms and definitions.
wait states that are programmed in the Bus
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured at 1.5 V
Measured at 1.5 V
0.8 V to 2.0 V
2.0 V to 0.8 V
†
Relative to TCK
Relative to TCK
for capacitive derating information
†
†
Notes
†
for capacitive
†
†
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