A80960HD80S L2GK Intel, A80960HD80S L2GK Datasheet - Page 74

• Manufacturer Part Number: A80960HD80S L2GK
• Manufacturer: Intel

Specifications of A80960HD80S L2GK

• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 80MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Compliant

80960HA/HD/HT
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Figure 49. BREQ and BSTALL Operation
The processor may stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted).
Depending on the instruction stream and memory wait states, the two signals may be separated by
several CLKIN cycles.
Bus arbitration logic that logically ‘ANDs’ BSTALL and BREQ will not correctly grant the bus to
the processor in all stall cases, potentially degrading processor performance.
Do not logically ‘AND’ BSTALL and BREQ together in arbitration logic. Instead, the simplest bus
arbitration should logically “OR” BSTALL and BREQ to determine the processor’s bus ownership
requirements.
More sophisticated arbitration should recognize the priority nature of these two signals. Using a
traffic light analogy, BREQ is a ‘yellow light’ warning of a possible processor stall and BSTALL is
a ‘red light’ indicating a stall in progress.
BSTALL
BLAST
CLKIN
BREQ
ADS
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