FW82371EB Q 657 Intel, FW82371EB Q 657 Datasheet
FW82371EB Q 657
Specifications of FW82371EB Q 657
Related parts for FW82371EB Q 657
FW82371EB Q 657 Summary of contents
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... Intel 82371EB (PIIX4E) Specification Update December 1999 ® Notice: The Intel 82371EB (PIIX4E) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. Order Number: 290635-008 ...
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... Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... R Contents Revision History............................................................................................................................4 Preface .........................................................................................................................................5 Specification Changes ................................................................................................................11 Errata ..........................................................................................................................................17 Specification Clarifications..........................................................................................................28 Documentation Changes ............................................................................................................41 Specification Update ® Intel 82371EB (PIIX4E) 3 ...
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... Intel 82371EB (PIIX4E) Revision History Date of Revision Version April 1998 -001 June 1998 -002 July 1998 -003 August 1998 -004 October 1998 -005 February 1999 -006 April 1999 -007 Jaunuary 2000 -008 4 Description Initial Release Added Errata #16 and Specification Clarification #20 ...
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... R Preface This document is an update to the specifications contained in the Intel (290562), and the Datasheet Addendum (273135), and contains issues affecting all designs using the Intel 82371EB (PIIX4E). This document is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. It contains Specification Changes, Errata, Specification Clarifications, and Documentation Changes ...
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... Intel 82371EB (PIIX4E) General Information This section covers the Intel ® Intel 82371EB (PIIX4E) Component Marking Information Stepping PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 PIIX4E A-0 ...
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... Summary Table of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications, or Documentation Changes which apply to the listed Intel® 82371EB (PIIX4E) steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted ...
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... Intel 82371EB (PIIX4E) NO. PIIX4 NO. PIIX4 PIIX4 PIIX4 PIIX4E PLANS DOC DOC PIIX4 PIIX4 PIIX4E PLANS NoFix NoFix NoFix X X NoFix X X Fix NoFix NoFix NoFix X X Fix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix SPECIFICATION CHANGES ...
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... DOC DOC X DOC DOC ® Intel 82371EB (PIIX4E) SPECIFICATION CLARIFICATIONS SUSA#, SUSB#, and SUSC# State Transition During Reset CONFIG[1] Definition IRQ8# Routing IRQ9 Routing SERIRQ Sample Phase RI# Pulse Width Requirement Diode Requirement for Vref Sequencing Circuit SMI# Generation from APMC Write ...
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... Intel 82371EB (PIIX4E) NO. PIIX4 PIIX4 PIIX4 PIIX4E PLANS DOC DOC DOC DOC DOC DOC DOC DOC DOC DOCUMENTATION CHANGES PCI Revision ID Register Values Interval Timer for IRQ0 Bus Master Activity for Burst Events IRQ9 and IRQ9OUT# Pin Locations PIO0 Timing Values ...
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... STPCLK# signal is asserted while in the throttle mode. The field is decoded as follows: Bits[2:0] 000 001 010 011 Specification Update 3Dh 00h Read only Description Base + (10h) 00h Read/Write Description Mode Bits[2:0] Reserved 100 87.5% 101 75% 110 62.5% 111 ® Intel 82371EB (PIIX4E) Mode 50% 37.5% 25% 12.5% 11 ...
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... Intel 82371EB (PIIX4E) 3. Enabling and Disabling Manual Throttling For the PIIX4, the manual throttling state is initiated by setting CC_EN, THT_EN and reading the LVL2 register. A break event will disable throttling and another LVL2 read is required to restart throttling. On the PIIX4E, break events will not disable manual throttling. Manual throttling mode begins when CC_EN and THT_EN are set ...
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... Deep Sleep state, the PIIX4 will defer all break events until the THRM# signal goes inactive. The PIIX4E will not defer break events based on the state of the THRM# signal. This change applies to all steppings of the PIIX4E and will be incorporated into the next revision of the PIIX4 datasheet. Specification Update Base + (0Eh) 00h Read/Write ® Intel 82371EB (PIIX4E) Description 13 ...
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... Intel 82371EB (PIIX4E) 6. Thermal Break Enable If THRM# is asserted for more than 2 seconds while the PIIX4 Stop Grant state, the PIIX4 will enter the thermal override state and begin throttling STPCLK# (see Specification Clarification #13). Once THRM# is deasserted the PIIX4 will return to the previous clock control state. If break events are disabled during the thermal override period the PiIIX4 will not be able to break out ...
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... The 82371AB (PIIX4) PCI ISA IDE Xcelerator Timing Specification, in Table 8 (PCI BUS IDE Timings) defines t115b as an 8nS min specification. This is specification is changed to 7nS min to meet ATA Specification data hold requirements. Specification Update 48-4Bh 00h Read/Write Description ® Intel 82371EB (PIIX4E) 15 ...
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... Intel 82371EB (PIIX4E) 14. VCC Specification Change The 82371AB (PIIX4) PCI ISA IDE Xcelerator Timing Specifications Document identifies the VCC range as 3.3v +/- .3V. This specification is changed to 3.3V +/- 5% for both the PIIX4 and the PIIX4E. 15. INTLN Register Not Implemented The PIIX4 Datasheet specified that the INTLN register contains interrupt information concerning the power management module ...
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... IDE device disabled, and the idle timer started the idle timer times out before the trap occurs, then the external IDE controller is idle and can be put into a lower power mode. The PIIX4 is then set up to trap below. Specification Update ® Intel 82371EB (PIIX4E) 17 ...
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... Intel 82371EB (PIIX4E the trap occurs first, the IDE device is not idle. The BIOS then returns to step b. above 3. If there is a need to perform I/O trapping on an external IDE controller, set the PIIX4 to trap on the IDE access and enable the PIIX4 internal IDE controller. When the SMI is generated, the internal IDE controller can be disabled, the external controller enabled, and the I/O cycle restarted ...
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... The Queue Head Link Pointer (QHLP=bits [31:4]) must be set to point to the pseudo TD. The QH/TD Select (Q=bit 1) must be set to 1 indicating QH. The Terminate bit (T=bit 0) must be set to 0 indicating that the link pointer field points to a valid TD. Specification Update ® Intel 82371EB (PIIX4E) 19 ...
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... This errata will be incorporated into the next revision of the PIIX4 Datasheet as a specification change. Intel is working with Microsoft* to incorporate the workaround into their UHCI driver. Microsoft* will make this workaround available in the Beta 1 release of Memphis. Microsoft* will provide a fix to the OSR2.1 (Detroit) release. OEMs/IHVs should contact Microsoft* for the fix distribution plans ...
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... Workaround: None. Status: This will not be fixed on PIIX4. This will be incorporated into the PIIX4 datasheet as a change to the specification. Specification Update / T ). The specification for a full speed device is 90% minimum and 110 CRS ® Intel 82371EB (PIIX4E) which is calculated by dividing Rise RFM) 21 ...
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... Intel 82371EB (PIIX4E) PCI Arbiter Advances when PC/PCI ISA Master Gets Retried by the Host 9. Controller Problem: When a PC/PCI ISA master cycle gets retried (delayed transaction) by the host controller, the PIIX4 PCI Arbiter advances to a pending PCI master (USB or IDE). Affects 440BX-PIIX4-MoonISA Docking platforms ...
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... ISA Legacy addresses 62 or 66h will also reload the times. NOTE: GPI4 is still available as a General Purpose Input. Workaround: None generic I/O device monitor exclusive of I/O address 62 and 66h is needed, then use Device 10 available. Status: This will not be fixed in the PIIX4E Specification Update ® Intel 82371EB (PIIX4E) 23 ...
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... Intel 82371EB (PIIX4E) USB Resume from Selective Suspend 14. Problem: A USB resume sequence signaled by a downstream device, from the PIIX4E, may not be properly detected by the PIIX4E if the USB clock is running and the USB port Selective Suspend mode. A combination of VCRS level and device speed (HS/LS) may allow the PIIXE to detect a SE1 level on a USB clock edge which the PIIX4E resume detect hardware cannot recognize ...
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... This erratum was observed during validation testing executing special test software. No reports from internal testing or customer testing on production systems (i.e. without special test software) have been attributed to this errata to date. Intel customers should perform there own risk analysis on this errata and determine the most appropriate work around for their systems. ...
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... Intel 82371EB (PIIX4E) C3 Power State/BMIDE & Type-F DMA Livelock Errata 18. Problem: The PIIX4E does not always correctly reflect BMIDE and Type-F DMA activity on the BMSTS bit in the Power Management Status Register (PMSTS) of PIIX4 Function 3. Implication: The Operating System will think that it is safe to enter a C3 state and will then disable the arbiter and then perform a PLVL3 register read to enter the C3 state, causing LIVELOCK to occur and resulting in a system hang ...
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... BIOS setup. 3) Contact your system provider to see if there is a BIOS update available that corrects this condition. Status: This will not be fixed in the PIIX4E. It will be corrected in future chipset implementations Specification Update ® Intel 82371EB (PIIX4E) 27 ...
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... Intel 82371EB (PIIX4E) Specification Clarifications SUSA#, SUSB#, and SUSC# State transition during RESET 1. After a hard reset (a write to C9h bit 2, with bit 1 set to 1) SUSA#, SUSC# immediately transition low for three to four RTC clocks. In many system designs, these signals control the various power plans. If the assertion of these signals do not affect the state of PWROK from the power supply circuitry, the hard reset completes normally with a system reboot ...
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... PIIX4’s GENCFG register will determine the configuration of PIIX4’s IRQ8# pin. Specification Update External RTS External APIC Not used Not used Not used Used Used Not used Used Used ® Intel 82371EB (PIIX4E) PIIX4’s IRQ Should be Selected as * GPI[6] (input) IRQ8# (output) IRQ8# (input) IRQ8# (input) 29 ...
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... Intel 82371EB (PIIX4E) IRQ9 Routing 4. SCI interrupts, SMBus interrupts and PIRQs can be routed to IRQ9. Any time an SCI, SMB or PIRQ is programmed to use the internal 8259’s IRQ9, the PIIX4 will ignore the ISA IRQ9 and the interrupts will behave like level triggered interrupts. The table below describes the implications of the different routing options ...
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... Figure 2, in section 2.3, of the PIIX4 datasheet provides an example Vref Sequencing Circuit. Included in this circuit is a diode. The datasheet does not explicitly state that this diode should be a Schottky diode. This clarification applies to all steppings of the PIIX4 and will be incorporated into the next revision of the PIIX4 datasheet. Specification Update ® Intel 82371EB (PIIX4E) 31 ...
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... Intel 82371EB (PIIX4E) SMI# Generation from APMC Write 8. In order to generate an SMI# by reading from the APMC Register it is necessary to enable both the APMC_EN bit as well as the IOSE bit. The datasheet section 4.2.6.1, 7.1.3, and 7.1.16 does not state that it is necessary to set the IOSE bit. ...
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... This bit is set when the internal RTC asserts its IRQ8 signal and the RTC_EN bit is set. This bit is only set by hardware and can only be reset by writing a one to this bit position. Specification Update Base + (00h) 00h Read/Write Description Base + (00h) 00h Read/Write Description ® Intel 82371EB (PIIX4E) 33 ...
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... Intel 82371EB (PIIX4E) SCI_EN Bit Clarification 11. The SCI_EN bit in the PMCNTRL register enables the generation of SCI from 4 sources; PWRBTN#, LID, THRM#, and GPI1#. If this bit is enabled and the individual enable bits from these sources are set (PWRBTN_EN, LID_EN, THRM_EN, and GPI_EN), an SCI is generated. If this bit is disabled and the individual enable bits from these sources are set, an SMI# is generated ...
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... The following should be added to the description of RSMRST#. It will reset the SM Bus Host and Slave controllers in the suspend well and will assert SUS[A:C]#. The assertion of SUS[A-C]# will generally initiate the deassertion of PWROK. RSMRST# assertion will then generally reset the entire system. Specification Update ® Intel 82371EB (PIIX4E) 35 ...
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... Intel 82371EB (PIIX4E) SMBus Busy Bit Behavior 20 polling environment, when reading the SMBus Host Status Register, the Host BUSY bit may appear to indicate a premature transaction completion. Though the Host BUSY bit accurately tracks the SMBus activity, there can be some delay between setting the start bit within the SMBus Controller and the transaction actually starting ...
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... SMBus Interrupt/Host Completion status bit going active. Specification Update Base + (02h) 00h Read/Write Description Protocol Bits[4:2] Quick Read or Write Byte Read or Write Byte Data Read or Write Word Data Read or Write ® Intel 82371EB (PIIX4E) Protocol 100 Reserved 101 Block Read or Write 110 Reserved 111 Reserved 37 ...
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... Intel 82371EB (PIIX4E) The SMBus controller will not respond to the START bit being set unless all interrupt status bits in the SMBHSTSTS register have been cleared. For Block Read or Block Write protocols, the data is stored in a 32-byte block data storage array. This array is addressed via an internal index pointer ...
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... CPU intermediarycircuitry which may also miss the short de- assertion pulse described below. Please consult the Microprocessor Specification v1.4 available on developer.intel.com for details on these operating modes. A high priority interrupt occuring just as the PiiX4E receives INTACK for a preceding low priority interrupt can cause a small interrupt de-assertion time from the new PiiX4E ( ...
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... Intel 82371EB (PIIX4E) To address the Virtual Wire Mode through the IO APIC problem, configure Virtual Wire mode to operate through the processor’s local APIC, vs. the IO APIC, and also for level triggered mode via EXTInt (default). A workaround for OS/2 has been identified for the anomaly. The OS/2 driver uses an environment variable switch to force the change to the correct virtual wire mode. The variable in config.sys is: Locate PSD=OS2APIC.PSD statement and add “ ...
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... This change applies to all steppings of the PIIX4 and will be incorporated into the next revision of the PIIX4 datasheet. Specification Update Stepping PIIX4 A-0 PIIX4 A-1 00h 00h 00h 00h 00h 00h 00h 00h ® Intel 82371EB (PIIX4E) PIIX4 B-0 PIIX4E A-0 01h 02h 01h 01h 01h 01h 01h 02h 41 ...
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PIO0 Timing Values 5. Table 14 in the PIIX4 Datasheet incorrectly lists the PIO0 cycle time, IORDY Sample Point and Recovery Time. The IORDY sample time is 6 clocks, the Recovery Time is 14 clocks, the 30 MHz cycle time ...
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... Pin M18 should be listed as PWROK INIT Assertion Correction 12. The PIIX4 Datasheet, section 2.1.6, on page 26, describes INIT as remaining asserted for approximately 64 PCI clocks before being negated. This is actually 16 PCI clocks, which is consistent with other discussion on this signal. Specification Update ® Intel 82371EB (PIIX4E) 43 ...
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... Intel 82371EB (PIIX4E) Corrections to Simplified Block Diagram, Table 55, and Figure 34 The PIIX4 Datasheet, Simplified Block Diagram, on page 3, the PIIX4 Pinout on page 270, and Table 55, starting on page 271, have several typographical errors. These are identified below. Simplified Block Diagram Corrections PHLKA# should be labeled as PHLDA# ...
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