FW82371EB Q 657 Intel, FW82371EB Q 657 Datasheet - Page 19

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FW82371EB Q 657

Manufacturer Part Number
FW82371EB Q 657
Description
Manufacturer
Intel
Datasheet

Specifications of FW82371EB Q 657

Lead Free Status / RoHS Status
Not Compliant
4.
Problem:
Implication: The USB host controller stops transferring data on the USB bus. The non-USB functions in the system
Workaround: When using bandwidth reclamation, the UHCI driver should insert a pseudo queue head with a pseudo
Specification Update
R
USB Bandwidth Reclamation Errata
This errata affects data transfers in conjunction with a UHCI driver utilizing bandwidth reclamation. In a
data structure which implements bandwidth reclamation, when all the queue heads have their terminate
bit set (empty QH’s), the USB subsystem will be unable to read a new frame pointer and will
continuously loop through the bandwidth reclamation queue heads. The effect of the errata is that the
USB subsystem will continue to send out Start Of Frame packets but transfer no data. On the PCI bus the
PIIX4 will continuously read the queue heads within the bandwidth reclamation loop. For additional
information on PIIX4 host controller operation refer to the Universal Host Controller Interface (UHCI)
Design Guide (order number 297650).
will continue to operate normally.
transfer descriptor within the bandwidth reclamation loop. The PIIX4 will fetch this queue head and
transfer descriptor on every frame, but will not transfer any data and will never be terminated. The
following bits must be properly set to implement the workaround:
TD LINK POINTER (DWORD 0: 00-03h)
The Link Pointer (LP=bits [31:4]) must be set to point to itself.
The Depth/Breadth Select bit (Vf=bit 2) must be set to 0 indicating that the PIIX4 should execute
breadth first.
The QH/TD Select (Q=bit 1) must be set to 0 indicating it is a TD.
The Terminate bit (T=bit 0) must be set to 0 indicating that the link pointer field is valid.
TD CONTROL AND STATUS (DWORD 1: 04-07h)
The Active status bit (bit 23) must be left unset at 0 indicating that the PIIX4 should not execute this TD.
QUEUE HEAD LINK POINTER (DWORD 0: 00-03h)
The Queue Head Link Pointer (QHLP=bits [31:4]) must be set to point to the pseudo TD.
The QH/TD Select (Q=bit 1) must be set to 1 indicating it is a QH.
The Terminate bit (T=bit 0) must be set to 0 indicating that the link pointer field points to a valid TD.
Intel
®
82371EB (PIIX4E)
19

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