FW82371EB Q 657 Intel, FW82371EB Q 657 Datasheet - Page 17

• Manufacturer Part Number: FW82371EB Q 657
• Manufacturer: Intel

Specifications of FW82371EB Q 657

• Lead Free Status / RoHS Status: Not Compliant

Errata
1.
Problem:
Implication: When the above conditions occur, the system will not transition into the Level 2 or Level 3 clock control
Workaround: Software must ensure that no external burst events are active when placing the system into a LVL2 or
Status:
2.
Problem:
Implication: Power management of external PCI-based IDE devices must use other means to monitor the activity of
Workaround: System BIOS should use the following methods to monitor external PCI-based IDE devices:
Specification Update
R
Burst Events May Cause LVL2 or LVL3 Register Reads to be Missed
Burst events that occur after Burst Enable bit (BST_EN) has been set and before the Processor Level 2
(LVL2) or Processor Level 3 (LVL3) register read may cause the LVL2 or LVL3 read to be missed.
condition as intended but will remain at full speed
LVL3 state. To ensure this, prior to LVL2 or Software must ensure that no external burst events are
active when placing the system into a LVL2 or LVL3 state. To ensure this, prior to LVL2 or LVL3
register read, only the Device 3 idle timer should be enabled as a burst event. The device 3 idle timer is
then enabled with all reload events disabled. The LVL2 or LVL3 register read is performed placing the
system into a LVL2 or LVL3 clock control condition. The Device 3 idle timer will then generate a burst
event upon expiration. During this first burst, the desired burst events are then enabled. The system then
functions as expected.
This will not be fixed in PIIX4. This was incorporated into the PIIX4 datasheet as a change to the
specification.
PCI accesses to External PCI-based IDE Devices will not cause Power
Management Events
PCI accesses to external IDE devices on the PCI bus do not generate power management events (Idle
timer reloads, global standby timer reloads, burst timer reloads, I/O traps).
those devices.
1. If there is a need to monitor accesses to the IDE controller to keep the global standby timer from
2. If there is a need to monitor an external IDE controller for idleness, use the following algorithm:
expiring, then the IRQs should be enabled (GRLD_EN_IRQ) as a reload event for the global standby
timer.
a. Disable the external IDE controller. Set the PIIX4 to trap on the IDE access and enable the
b. When the SMI is generated, the idle timer can be started, the internal IDE controller disabled, and
c. When the idle timer times out, an SMI is generated and the PIIX4 should again be set to trap, the
d. If the idle timer times out before the trap occurs, then the external IDE controller is idle and can be
the instruction redone to the external IDE controller. The IDE device is then assumed to be active
during idle timer count down.
external IDE device disabled, and the idle timer started.
internal IDE controller.
put into a lower power mode. The PIIX4 is then set up to trap as in 3. below.
Intel
®
82371EB (PIIX4E)
17