PNX1700EH/G,557 Trident Microsystems, Inc., PNX1700EH/G,557 Datasheet - Page 436

• Manufacturer Part Number: PNX1700EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1700EH/G,557

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Philips Semiconductors
Volume 1 of 1
1.
PNX17XX_SER_1
Preliminary data sheet
For compatibility with 8-bit D1 interfaces the two LSBs are not used for timing reference extraction (as defined in CCIR 656-2).
2.4 Input Formats
To capture a picture using the build-in test pattern generator (odd and even field), set
up the registers as shown in
white frame.
Table 2: Test Pattern Generator Setup
The VIP accepts the following external video input streams:
The YUV 4:2:2 sampling scheme assumed by all modes is defined by CCIR 601.
D1 Mode
The D1 Mode expects an 8/10-bit 4:2:2 video data stream (defined by CCIR 656) with
syncs encoded in the video data stream.
80h, 9Dh, ABh, B6h, C7h, DAh, ECh and F1h. Single bit errors in the reference codes
are corrected, but double bit errors are rejected. The supported mode is shown in
Figure
Mode
NTSC
PAL
Figure 4:
–
–
–
–
8/10-bit data with encoded [EAV/SAV] syncs YUV 4:2:2 (alias D1 mode)
8-bit data with external [HREF, VREF] syncs YUV 4:2:2 (alias VMI mode)
8/10-bit or 16/20-bit raw data samples (alias RAW mode)
16/20-bit video data on 2 groups of pins for Y and multiplexed U/V with both
encoded [SAV/EAV] and explicit [hrefhd, vrefhd, frefhd] syncs (alias
DUAL_STREAM or HD mode)
5.
Test Pattern
Reference
HREF- / VREF+
HREF- / VREF+
Rev. 1 — 17 March 2006
Table 2
to start capturing at the upper left corner of the
Window Start (x,y)
8a,0 (138,0)
90,0 (144,0)
1
Timing reference codes recognized are
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Window End (x,y)
359,f1 (857,241)
35f,11f (863,287)
12-5