PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 63

• Manufacturer Part Number: PNX1311EH/G
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G

• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
• functional units should be ‘recovered’ from any prior
Writeback constraint:
• No more than 5 results should be simultaneously
Figure 3-3
ing the relation to issue slots, and each functional unit’s
latency (e.g. 1 for CONST, 3 for FALU, etc.). With the ex-
ception of FTOUGH, each functional unit can accept an
operation every clock cycle, i.e. has a recovery time of 1.
The binding of operations to functional unit types is sum-
marized in
11 DSPCPU
cise functional unit and unit latency.
Table 3-8. Functional unit operations
3.4
PNX1300 defines four apertures in its 32-bit address
space: the memory hole, the DRAM aperture, the MMIO
aperture and the PCI apertures (See
memory hole covers addresses 0..0xff. The DRAM and
MMIO apertures are defined by the values in MMIO reg-
isters; the PCI apertures consist of every address that
does not fall in the other three apertures.
3.4.1
DRAM is mapped into an aperture extending from the
address
DRAM_LIMIT. The maximum DRAM aperture size is 64
MB.
The MMIO aperture is located at address MMIO_BASE
and is a fixed 2-MB size.
In the default operating mode, all memory accesses not
going to either the hole, DRAM or MMIO space are inter-
preted as PCI accesses. This behavior can be overrid-
den as described in
PCI Aperture Disable.”
The MMIO aperture and the DRAM aperture can be at
any naturally aligned location, in any order, but should
const
alu
dspalu
dspmul
dmem
dmemspec
shifter
branch
falu
ifmul
fcomp
ftough
unit type
operation issues
written to the register file at any point in time (write-
back occurs ‘latency’ cycles after issue)
MEMORY AND MMIO
Memory Map
shows all functional units of PNX1300, includ-
in
Table
immediate operations
32-bit arithmetic, logical, pack/unpack
dual 16-bit, quad 8-bit multimedia arithmetic
dual 16-bit and quad 8-bit multimedia multiplies
loads/stores
cache coherency, cache control, prefetch
multi-bit shift
control flow
floating point arithmetic & conversions
32-bit integer and floating point multiplies
single cycle floating point compares
iterative floating point square root and division
Operations”, each operation lists the pre-
DRAM_BASE
3-8. In
Section 5.3.8, “Memory Hole and
Appendix A, “PNX1300/01/02/
operation category
to
the
Figure
address
3-4).The
in
not overlap; if they do, the consequences are undefined.
The values of DRAM_BASE, DRAM_LIMIT, and
MMIO_BASE are set during the boot process. In the
case of a PCI host assisted boot, the values are deter-
mined by the host BIOS. In case of standalone boot (i.e.,
PNX1300 is the PCI host), the values are taken from the
boot ROM. Refer to
tails.
MMIO_BASE is possible, but not recommended, see
Section 11.6.3, “MMIO/DRAM_BASE updates.”
3.4.2
The memory hole from address 0 to 0xff serves to protect
the system from performance loss due to speculative
loads. Due to the nature of C program references, most
speculative loads issued by the DSPCPU fall in the
range covered by the hole. Activated by default upon RE-
SET, the hole serves to ensure that these speculative
loads do NOT cause PCI read accesses and slow down
the system. The value returned by any data load from the
hole is 0. The hole only protects loads. Store operations
in the hole do cause writes to PCI, SDRAM or MMIO as
determined by the aperture base address values. If the
SDRAM aperture overlaps the memory hole, the memory
hole is ignored.
The hole can be temporarily disabled through the
DC_LOCK_CTL register. This is described in
5.3.8, “Memory Hole and PCI Aperture Disable.”
3.4.3
Devices are controlled through memory-mapped device
registers, referred to as MMIO registers. To ensure com-
patibility with future devices, any undefined MMIO bits
should be ignored when read, and written as ‘0’s. Some
devices can autonomously access data memory (DMA)
and most devices can cause CPU interrupts.
The 2-MB MMIO aperture is initially located at address
0xEFE00000 on RESET; it is relocated by the PCI BIOS
Figure 3-4. PNX1300 memory map.
PRELIMINARY SPECIFICATION
0xFFFF FFFFF
DSPCPU
DRAM_BASE
DRAM_LIMIT
MMIO_BASE
0x0000 0000
The Memory Hole
MMIO Memory Map
update
Chapter 13, “System Boot”
2 MB
1 MB - 64 MB
256byte
DRAM Aperture
MMIO Aperture
hole
DSPCPU Architecture
PCI
PCI
PCI
of
DRAM_BASE
Section
for de-
and
3-7