SAA7111AHZV4 NXP Semiconductors, SAA7111AHZV4 Datasheet - Page 37
SAA7111AHZV4
Manufacturer Part Number
SAA7111AHZV4
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7111AHZV4.pdf
(72 pages)
Specifications of SAA7111AHZV4
Pin Count
64
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
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Philips Semiconductors
Notes to Table 5
1. VPO bus allows connection to 5 V video data bus systems.
2. Values in accordance with CCIR 601.
3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656.
4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit
5. CREF = 0 (see Fig.17).
6. CREF = 1 (see Fig.17).
1998 May 15
handbook, full pagewidth
Enhanced Video Input Processor (EVIP)
CCIR Rec. 602 digital levels.
Equations for modification to the YUV levels via BCS control I
Luminance:
Chrominance:
It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Y
UV
a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I
b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I
signals (after dithering if desired).
OUT
OUT
=
=
Int
Int
CONT
----------------- -
SATN
---------------- -
71
255
235
128
64
16
0
a.
LUMINANCE 100%
Y 128
Y output range.
Cr Cb 128
–
–
+
Fig.28 VPO output signal range with default BCS settings.
BRIG
+
white
black
128
255
240
212
128
44
16
0
b.
U-COMPONENT
2
C-bus bytes BRIG, CONT and SATN.
U output range (Cb).
37
2
colourless
C-bus bit TCLO = 0
blue 100%
yellow 100%
blue 75%
yellow 75%
2
C-bus bit TCLO = 1.
212
255
240
128
44
16
0
c.
V-COMPONENT
V output range (Cr).
colourless
red 100%
red 75%
cyan 100%
cyan 75%
Product specification
MGC634
SAA7111A
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