LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 15

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Pseudo Dual-Port SRAM Mode
In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and
write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.
Write data, write address, chip select and write enable signals are always synchronous (registered). The read data
and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the
same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both
read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for
the various registers.
Figure 10. Pseudo Dual-Port SRAM Block Diagram
Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode
Write Address, Write
Data, Write Enable,
and Write Chip Select
Read Data and Read
Address
Register
Clock
Clock Enable
Reset
Clock
Clock Enable
Reset
RESET
CLK0
CLK1
CLK2
CLK3
68 Inputs
Input
Routing
From
Write Enable
Write Clock
Write Chip Sel
Write Clk Enable
Read Clk Enable
Read Clock
Reset
Write Address
(WAD[0:8-13])
Write Data
(WD[0:0,1,3,7,15,31])
WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can
be inverted if desired.
WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be
inverted if desired.
RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
Read Address
(RAD[0:8-13])
(RST)
(RCLK)
(WCLK)
(WE)
(WCS[0,1])
11
(WCEN)
(RCEN)
‘
‘
16,384 bit
Pseudo
SRAM
Array
Dual
Port
ispXPLD 5000MX Family Data Sheet
Source
Read Data
(RD[0:0-15])