LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 17

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
FIFO Mode
In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The
read and write clocks can be different or the same dependent on the application. Four flags show the status of the
FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are pro-
grammable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communica-
tions applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read
address.
In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 12 shows the block diagram of the FIFO.
Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share
the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead
mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared
by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various reg-
isters.
Figure 12. FIFO Block Diagram
Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode
Write Data,
Write Enable
Full and
Almost Full
Flags
Read Data,
Empty and
Almost Empty
Flags
Register
Clock
Clock
Enable
Reset
Clock
Clock
Enable
Reset
Clock
Clock
Enable
Reset
Input
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
N/A
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
RESET
CLK0
CLK1
CLK2
CLK3
68 Inputs
Routing
From
Write Enable
Read Clock
Reset_RP
Read Enable
*Control logic can be
duplicated in adjacent MFB
in 32-bit mode
Write Data
(DI[0:0-31])
Write Clock
Reset
(RST)
(RSTRP)
(RCLK)
(WCLK)
(RE)
(WE)
13
‘
‘
16,384-bit
Control
Logic
SRAM
FIFO
Array
Source
ispXPLD 5000MX Family Data Sheet
Al m ost Empty
Read Data
Full, Empty,
Almost Full,
Flags*
(DO[0:0-31])
FIFO