LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 49
LC5512MV-75F256C
Manufacturer Part Number
LC5512MV-75F256C
Description
CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LC5512MV-75FN256C.pdf
(99 pages)
Specifications of LC5512MV-75F256C
Package
256FBGA
Family Name
ispXPLDÂ 5000MV
Device System Gates
150000
Number Of Macro Cells
512
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
193
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
150 MHz
Number Of Product Terms Per Macro
160
Ram Bits
262144
Memory Type
EEPROM/SRAM
Operating Temperature
0 to 90 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC5512MV-75F256C
Manufacturer:
LATTICE
Quantity:
190
Company:
Part Number:
LC5512MV-75F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC5512MV-75F256C
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
Lattice Semiconductor
Boundary Scan Timing Specifications
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BTCP
BTCPH
BTCPL
BTS
BTH
BTRF
BTCO
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
Parameter
TCK [BSCAN] clock pulse width
TCK [BSCAN] clock pulse width high
TCK [BSCAN] clock pulse width low
TCK [BSCAN] setup time
TCK [BSCAN] hold time
TCK [BSCAN] rise/fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
Over Recommended Operating Conditions
Description
45
ispXPLD 5000MX Family Data Sheet
Min
40
20
20
10
50
—
—
—
10
—
—
—
8
8
Max
10
10
10
25
25
25
—
—
—
—
—
—
—
—
mV/ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns