SCAN926260TUF National Semiconductor, SCAN926260TUF Datasheet - Page 16

• Manufacturer Part Number: SCAN926260TUF
• Manufacturer: National Semiconductor

Specifications of SCAN926260TUF

• Number Of Elements: 6
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 50mV
• Diff. Input Low Threshold Volt: -50mV
• Output Type: Deserializer
• Transmission Data Rate: 660Mbps
• Power Dissipation: 3.7W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: LBGA
• Number Of Receivers: 1
• Number Of Drivers: 10
• Lead Free Status / RoHS Status: Not Compliant

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GND
R
N/C
DVdd
DGND
PVdd
PGND
AVdd
AGND
PWRDWN [0:5]
MS_PWRDWN
REN
REFCLK
LOCK[0:5]
ROUTn[0:9]
RCLK[0:5]
INn
Pin Descriptions
±
Pin Name
3.3V CMOS
3.3V CMOS
3.3V CMOS
3.3V CMOS
3.3V CMOS
3.3V CMOS
3.3V CMOS
Bus LVDS
Output
Output
Output
Type
GND
Input
Input
Input
Input
Input
B2, B14, L4, L5
A3-A4, A6-A7, A9-10, C5-
C6, C8-C9, C10-C11
E3
B1, B3, C4, D6, D12, E6,
E7, E9, E10, F7, F10, F12,
G6, G10, H6, H10, J5, J8,
J9, J10, K5, K6, K7, K10,
L10
A1, D4, D5, D7, D9, D11,
E5, E8, F5, F6, F8, F9, G5,
G7, G8, G9, H5, H7, H8, H9,
J6, J7, K8, K9, L7
E1, F1, F14, G14, J1, J14,
K1, K14,P5, P6, P9, P10
A14, B12, D10, G1, G2,
G13, H1, H13, H14, J4, J13,
N7, N8, P7, P8
A11, B6, B9, C7
A5, A8, B7, B8, B11
A12, A13, C3, C12, E11,
F11
B5
A2
B4
D13, F3, N3, P1, P12, P13
E2, E4, E12, E13, E14, F4,
G3, G4, G11, G12, H2, H3,
H4, H11, H12, J2, J3, J11,
J12, K2, K3, K4, K12, K13,
L1, L3, L6, L8, L9, L11, L12,
L13, L14, M1, M2, M3, M4,
M5, M6, M7, M8, M9, M10,
M11, M12, M14, N1, N2,
N4, N6, N9, N11, N12, N13,
N14, P2, P3, P4, P11, P14
F2, F13, L2, M13,N5, N10
Pins
16
Ground pins for ESD structures.
Bus LVDS differential input pins. Failsafe described in Application
Information section.
This pin is not bonded out. Therefore, you may tie this pin High,
Low, or as a N/C. However, for board layout compatibility with the
SCAN921260 or the DS92LV1260, tie this pin LOW.
Supply voltage for digital section.
Ground pins for digital section.
Supply voltage for PLL circuitry.
Ground pins for PLL circuitry.
Supply voltage for analog circuitry.
Ground pins for analog circuitry.
A low on one of these pins puts the corresponding channel into
sleep mode and a high makes the corresponding channel active.
There is an internal pull-down on each of these pins that defaults
the PWRDWNn input to sleep mode. Active operation requires
asserting a high on the PWRDWNn and MS_PWRDWN input.
A low on this pin puts the device into sleep mode and a high
makes the part active. There is an internal pull-down that defaults
the MS_PWRDWNn input to sleep mode. Active operation
requires asserting a high on the MS_PWRDWNn input.
Enables the ROUTn[0:9], RCLKn, outputs. There is an internal
pull-down that defaults REN to TRI-STATE the outputs. Active
outputs require asserting a high on REN. Please note that
LOCKn is not affected by REN.
Frequency reference input. Used by the PLL while locking onto
incoming LVDS streams.Has no phase relation to RCLK.
Indicates the status of the PLLs for the individual deserializers:
LOCKn= L indicates locked, LOCKn= H indicates unlocked.
Outputs for the ten bit deserializers; n = deserializer number.
When a channel is not locked, ROUT[0:9] are high for that
channel.
Recovered clock for each deserializer's output data. When a
channel is not locked, the RCLK for that channel is high.
Description