SCAN926260TUF National Semiconductor, SCAN926260TUF Datasheet - Page 3
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SCAN926260TUF
Manufacturer Part Number
SCAN926260TUF
Description
Manufacturer
National Semiconductor
Datasheet
1.SCAN926260TUF.pdf
(20 pages)
Specifications of SCAN926260TUF
Number Of Elements
6
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Differential Input High Threshold Voltage
50mV
Diff. Input Low Threshold Volt
-50mV
Output Type
Deserializer
Transmission Data Rate
660Mbps
Power Dissipation
3.7W
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
LBGA
Number Of Receivers
1
Number Of Drivers
10
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SCAN926260TUF
Manufacturer:
SONY
Quantity:
69
Company:
Part Number:
SCAN926260TUF
Manufacturer:
NS
Quantity:
560
Company:
Part Number:
SCAN926260TUF
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
SCAN926260TUF
Manufacturer:
NS/国半
Quantity:
20 000
Company:
Part Number:
SCAN926260TUF/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Company:
Part Number:
SCAN926260TUFX
Manufacturer:
Texas Instruments
Quantity:
10 000
Company:
Part Number:
SCAN926260TUFX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Supply Current
I
ΔI
I
Timing Requirements for REFCLK
t
t
t
t
Deserializer Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CCR
CCXR
RFCP
RFDC
RFCP
RFTT
RCP
RDC
CLH
CHL
ROS
ROH
HZR
LZR
ZHR
ZLR
DD
DSR1
DSR2
RNMI-RIGHT
RNMI-LEFT
Symbol
CCR
/t
TCP
Total Supply Current
Reduction in Supply
Current per Channel
Total Supply Current
when Powered Down
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK
REFCLK Transition
Time
RCLK Period
RCLK Duty Cycle
LVCMOS/LVTTL Low-
to-High Transition Time
LVCMOS/LVTTL High-
to-Low Transition Time
Rout Data Valid before
RCLK
Rout Data Valid after
RCLK
High to TRI-STATE
Delay
Low to TRI-STATE
Delay
TRI-STATE to High
Delay
TRI-STATE to Low
Delay
Deserializer Delay
Deserializer PLL LOCK
Time from PWRDNn
(with SYNCPAT)
Deserializer PLL Lock
Time from SYNCPAT
Deserializer Right
Noise Margin
Deserializer Left Noise
Margin
Parameter
66 MHz Only
Checker Board
Checker Board
MS_PWRDN=
Conditions
(All Cases)
C
PRBS-15
C
C
Figure 3,
Figure 2
Figure 2
Figure 7
Figure 1
Figure 4
Figure 5
Figure 8
Pattern,
Pattern,
(Note 4)
(Note 5)
(Note 6)
(Note 7)
(Note 7)
(Note 8)
L
Pattern
L
L
0.8V,
= 15pF,
=15pF
=15pF
Pin/Freq.
66 MHz
66 MHz
66 MHz
66MHz
16MHz
66MHz
16MHz
66MHz
16MHz
66MHz
16MHz
LOCK,
RCLK,
ROUT
RCLK
RCLK
3
1.75*t
1.75*t
-0.4*t
0.4*t
15.15
15.15
0.95
Min
400
440
1.3
1.0
1.3
1.4
55
30
41
RCP
RCP
RCP
RCP
+5
+6
1.75*t
1.75*t
2.51
2.59
Typ
500
385
500
600
1.5
1.8
1.5
77
50
50
RCP
RCP
+7
+7
1.75*t
1.75*t
Max
62.5
1.05
62.5
600
100
2.2
2.2
2.0
2.5
7.0
1.1
4.5
70
55
10
10
12
12
8
RCP
RCP
www.national.com
+10
+9
Units
mA
mA
mA
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ps
ns
ps
ns
%
%