SCAN926260TUF National Semiconductor, SCAN926260TUF Datasheet - Page 9

• Manufacturer Part Number: SCAN926260TUF
• Manufacturer: National Semiconductor

Specifications of SCAN926260TUF

• Number Of Elements: 6
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 50mV
• Diff. Input Low Threshold Volt: -50mV
• Output Type: Deserializer
• Transmission Data Rate: 660Mbps
• Power Dissipation: 3.7W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: LBGA
• Number Of Receivers: 1
• Number Of Drivers: 10
• Lead Free Status / RoHS Status: Not Compliant

Initialization
Before the SCAN926260 receives and deserializes data, it
and the transmitting Serializer must initialize the link. Initial-
ization refers to synchronizing the Serializer's and the
Deserializer's PLL's to local clocks. The local clocks must be
within ±5% of the incoming transmitter clock frequency. After
all devices synchronize to local clocks, the Deserializer syn-
chronizes to the Serializer as the second and final initialization
step.
Step 1: After applying power to the Deserializer, the outputs
are held high and the on-chip Power-on Reset (POR) circuitry
disables the internal circuits. When V
the PLL in each deserializer begins locking to the local clock
(REFCLK). A local on-board oscillator or other source that
provides the specified clock input to the REFCLK pin.
Step 2: The Deserializer PLL must synchronize to the Serial-
izer to complete the initialization. Refer to the Serializer data
sheet for proper operation during the Initialization State. The
Deserializer identifies the rising clock edge in a synchroniza-
tion pattern or pseudo-random data and after 80 clock cycles
will synchronize to the data stream from the Serializer. At the
point where the Deserializer's PLL locks to the embedded
clock, the LOCKn pin goes low and valid data appears at the
outputs.
Data Transfer
After initialization, the Serializer transfers data to the Deseri-
alizer. The serial data stream includes a start and stop bit
appended by the serializer, which frames the ten data bits.
The start bit is always high and the stop bit is always low. The
start and stop bits also function as clock bits embedded in the
serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at
12 times the TCLK frequency. For example, if TCLK is 40
MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits
are from input data, the serial 'payload' rate is 10 times the
TCLK frequency. For instance, if TCLK = 40 MHz, the payload
data is 40 X 10 = 400 Mbps. TCLK is provided by the data
source and must be in the range of 16MHz to 66MHz.
When one of six Deserializer channels synchronizes to the
input from a Serializer, it drives its LOCKn pin low and syn-
chronously delivers valid data at its outputs. The Deserializer
locks to the embedded clock, uses it to generate multiple in-
ternal data strobes, and drives the embedded clock to the
RCLKn pin. The RCLKn pin is synchronous to the data on the
ROUTn[0:9] pins. While LOCKn is low, data on ROUTn[0:9]
is valid. Otherwise, ROUTn[0:9] and RCLKn are high.
All ROUT, LOCK, and RCLK signals will drive a minimum of
three CMOS input gates (15pF load) with a 66 MHz clock.
This amount of drive allows bussing outputs of two Deserial-
izers and a destination ASIC. REN controls TRI-STATE of all
the outputs.
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reaches V
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OK (2.1V),
9
The Deserializer input pins are high impedance during Pow-
erdown (PWRDNn or MS_PWRDN low) and power-off (V
0V).
Resynchronization
Whenever one of the six Deserializers loses lock, it will auto-
matically try to resynchronize. For example, if the embedded
clock edge is not detected two times in succession, the PLL
loses lock and the LOCKn pin is driven high. The system must
monitor the LOCKn pin to determine when data is valid.
The user has the choice of allowing the deserializer to re-sync
to the data stream or to force synchronization by asserting the
Serializer SYNC1 or SYNC2 pin high. This scheme is left up
to user discretion. One recommendation is to provide a feed-
back loop using the LOCKn pin itself to control the sync
request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins
are provided for local or remote control..
Powerdown
The Powerdown state is a low power sleep mode that the
Deserializer typically occupies while waiting for initialization
or to reduce power consumption when no data is transferred.
While in Powerdown Mode, the PLL stops and RCLK and
ROUTn[0:9] are high, which reduces the supply current for
each channel by approximately 80mA. Each channel has a
powerdown (PWRDWNn) pin that puts the respective chan-
nel into sleep mode when asserted low. In addition, the
SCAN926260 has a master powerdown (MS_PWRDWN) pin
that overrides each individual powerdown pin and puts the
entire device into sleep mode when asserted low (This same
condition can be replicated by asserting all six individual pow-
erdown pins low.). The powerdown pins are internally pulled
low which defaults the device into sleep mode. Active opera-
tion requires asserting a high on MS_PWRDWN and the
selected channel’s PWRDWNn pin.
Upon exiting Powerdown, the Deserializer enters the Initial-
ization state. The system must then allow time to Initialize
before data transfer can begin.
TRI-STATE
When the system drives the REN pin low, the Deserializer
enters TRI-STATE. This will TRI-STATE the receiver output
pins (ROUTn[0:9]) and RCLK[0:5]. When the system drives
REN high, the Deserializer will return to the previous state as
long as all other control pins remain static (PWRDWNn,
MS_PWRDWN). The LOCKn pin is not affected by REN and
continues to be active, signalling LOCK status. This allows
the system to be sure the channel is locked before enabling
the data outputs.
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