3336-52 Peregrine Semiconductor, 3336-52 Datasheet - Page 3

• Manufacturer Part Number: 3336-52
• Description: IC PLL INTEGER-N 300MHZ 48-QFN
• Manufacturer: Peregrine Semiconductor

Specifications of 3336-52

• Function: Integer-N PLL
• Frequency: 3GHz
• Rf Type: General Purpose
• Secondary Attributes: Divide by 10,11
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1014-2

PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Document No. 70-0033-05 │ www.psemi.com
Pin No.
17,18
16
10
11
12
13
14
15
19
20
21
22
7
8
9
S_WR
D
M
Sdata
D
M
Sclk
D
M
FSELS
D
Pre_en
GND
FSELP
A
E_WR
A
M2_WR
A
Smode
A
Bmode
V
M1_WR
A_WR
Hop_WR
F
0
1
2
3
DD
in
4
5
6
7
4
5
6
Pin Name
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Direct
Serial
Parallel
Direct
Parallel
Direct
Serial, Parallel
Direct
ALL
ALL
Parallel
Parallel
Serial, Parallel
ALL
Interface Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Type
Serial load enable input. While S_WR is “low”, Sdata can be serially
clocked. Primary register data are transferred to the secondary register on
S_WR or Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
Ground.
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement
register on the rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface
Mode (Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on
the rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Description
in
bypasses the prescaler.
Page 3 of 13