3336-52 Peregrine Semiconductor, 3336-52 Datasheet - Page 4

• Manufacturer Part Number: 3336-52
• Description: IC PLL INTEGER-N 300MHZ 48-QFN
• Manufacturer: Peregrine Semiconductor

Specifications of 3336-52

• Function: Integer-N PLL
• Frequency: 3GHz
• Rf Type: General Purpose
• Secondary Attributes: Divide by 10,11
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1014-2

Table 1. Pin Descriptions (continued)
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 13
Notes: 1. All V
2. All digital input pins have 70 kΩ pull-down resistors to ground.
Pin No.
31,37
38,39
V
23
24
25
26
27
28
29
30
32
33
34
35
36
40
41
42
43
44
45
46
47
48
DD
-f
DD
p
and V
pins are connected by diodes and must be supplied with the same positive voltage level.
DD
-f
p
F
GND
f
V
Dout
V
Cext
V
PD_D
PD_U
NC
V
f
GND
GND
f
LD
Enh
V
R
R
R
R
GND
are used to power the f
p
c
r
in
DD
DD
DD
DD
DD
0
1
2
3
Pin Name
-f
-f
p
c
Interface Mode
ALL
ALL
ALL
ALL
Serial, Parallel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial, Parallel
ALL
Direct
Direct
Direct
Direct
ALL
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
Input
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Input
Output
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
Type
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50 Ω resistor
directly to the ground plane.
Ground.
Monitor pin for main divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding V
pin 31.
V
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
PD_D is pulse down when f
PD_U is pulse down when f
No connection.
V
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding V
pin 38.
Ground.
Ground.
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When the loop is in
lock, LD is high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits
are functional.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
DD
DD
for f
for f
p
c
. Can be left floating or connected to GND to disable the f
can be left floating or connected to GND to disable the f
Document No. 70-0033-05 │ UltraCMOS™ RFIC Solutions
p
c
leads f
leads f
Description
p
c
.
.
p
and f
c
outputs.
Product Specification
c
PE3336
p
output.
output.
DD
DD