3336-52 Peregrine Semiconductor, 3336-52 Datasheet - Page 9

• Manufacturer Part Number: 3336-52
• Description: IC PLL INTEGER-N 300MHZ 48-QFN
• Manufacturer: Peregrine Semiconductor

Specifications of 3336-52

• Function: Integer-N PLL
• Frequency: 3GHz
• Rf Type: General Purpose
• Secondary Attributes: Divide by 10,11
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1014-2

PE3336
Product Specification
input is “low”, serial input data (Sdata input), B
B
register on the rising edge of Sclk, MSB (B
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
5. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 with bit
functionality enabled by asserting the Enh input
“low”.
Table 7. Primary Register Programming
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
Table 8. Enhancement Register Programming
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Document No. 70-0033-05 │ www.psemi.com
Parallel
Interface
Serial*
Inter-
Mode
Direct
Parallel
face
Serial*
Mode
7
, are clocked serially into the enhancement
Enh
1
1
1
Enh
0
0
Bmode
0
0
1
Bmode
X
X
Smode
0
1
X
Smode
0
1
M2_WR rising edge load
R
D
B
0
5
3
0
MSB (first in)
Reserved
R
D
B
0
4
2
1
D
B
MSB (first in)
7
0
M
D
B
0
2
8
1
M
D
B
0
Reserved
0
3
7
D
B
Pre_en
Pre_en
0
6
1
) first.
D
B
7
4
0
to
M
M
D
B
Reserved
6
5
6
6
M1_WR rising edge load
D
B
M
D
M
5
2
B
6
5
5
5
M
M
D
B
4
7
4
4
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M
R
4
E_WR rising edge load
Power
down
M
D
M
B
and R
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
8
D
3
3
3
B
3
4
M
M
D
B
2
9
2
2
input “high”.
5
are internally forced low (“0”).
B
M
M
D
10
1
1
1
Counter
load
D
B
3
4
B
M
D
M
11
7
0
0
0
and M
B
R
D
R
12
3
7
3
B
output
R
D
R
MSEL
8
13
2
6
2
, and R Counter inputs
D
B
2
5
A_WR rising edge load
B
R
D
R
14
1
5
1
B
R
D
R
15
0
4
0
Prescaler
(last in) LSB
output
D
B
B
A
D
A
16
1
6
3
3
3
(last in) LSB
B
A
D
A
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17
2
2
2
B
f
A
D
A
c
18
, f
1
1
1
D
B
p
7
0
OE
B
A
D
A
19
0
0
0