XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 30

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 46
Table 46: Input Delay Measurement Methodology
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL, Class III
HSTL, Class I & II, 1.8V
HSTL, Class III 1.8V
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
HT (HyperTransport), 2.5V
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
values listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the V
The value given is the differential input voltage.
shows the test setup parameters used for measuring input delay.
Description
L
and V
H
.
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I, HSTL_II
HSTL_III
HSTL_I_18, HSTL_II_18
HSTL_III_18
SSTL3_I, SSTL3_II
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
LVDS_25
LVDSEXT_25
LDT_25
I /O Standard Attribute
www.xilinx.com
REF
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
REF
values. Reported delays reflect worst case of these measurements. V
/ V
MEAS
parameters found in IBIS models and/or noted in
V
V
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
V
L
(1)(2)
0
0
0
– 1.00
– 0.75
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V
V
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
V
H
2.5
1.8
1.5
(1)(2)
+ 1.00
+ 0.75
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
V
(1)(4)(5)
V
V
V
V
V
V
V
1.25
0.75
MEAS
0
0
0
0.9
REF
REF
REF
REF
REF
REF
REF
(6)
(6)
(6)
Figure
(1)(3)(5)
V
0.75
0.90
0.90
1.08
1.25
0.90
1.5
REF
–
–
–
–
–
–
6.
REF
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