XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 56

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Table 72: Sample Window
Table 73: Pin-to-Pin Setup/Hold and Clock-to-Out
Revision History
The following table shows the revision history for this document:
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
T
T
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T
Pin-to-Pin Clock-to-Out Using BUFIO
T
SAMP
SAMP_BUFIO
PSCS
ICKOFCS
06/24/09
07/16/09
08/19/09
09/16/09
This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Date
Symbol
/T
PHCS
Symbol
Version
Sampling Error at Receiver Pins
Sampling Error at Receiver Pins using
BUFIO
1.0
1.1
1.2
2.0
Setup/Hold of I/O clock
Clock-to-Out of I/O clock
(2)
Initial Xilinx release.
Revised the maximum V
Table 3, page
notes 1 and 2. Revised T
Updated
T
Table 69, page
Added values for -1L voltages and speed grade in all pertinent tables. Added V
and
Table 41, page
removing Note 12. Changed F
in
Added Virtex-6 HXT devices to entire document including
speed specifications as described in
Table
Table
specification and note from
LVCMOS25 delays in
from
TAPTCK
Table 63, page
Table
Table 70, page 54
Description
56,
16. Added conditions to D
/T
Table 57, page 41
Table
TCKTAP
2. Removed DV
2. Revised specifications on
23. Changed and added to the block RAM F
53.
57, and
Description
48. Updated
in
Table 58, page
(1)
Table
Table 65
and added values for T
CCAUX
DLYCCO_RDY
PPIN
www.xilinx.com
Table
to more closely match the DSP48E1 speed specifications. Updated
44. Updated specification for T
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
PFDMAX
Table 70, page
from the example in
and V
VPPOUT
through
18. Added note 3 to
44. Updated XC6VLX130T parameters in
, T
Description of Revisions
Switching
IN
Device
values and corrected units for T
IDELAYCTRL_RPW
and revised description of T
numbers in
All
All
Table
Table 20, page
54.
69. Comprehensive changes to
BUFIOSKEW
Characteristics, includes changes in
510
300
-3
Table 2, page
Figure
Table
–0.28
1.09
4.22
, and T
-3
. Added values in
GTH Transceiver
11. Updated
2. Added networking applications to
IOTPHZ
MAX
23. Updated note 3 in
560
350
Speed Grade
-2
IDELAYPAT_JIT
section in
–0.28
2. Removed empty column from
1.16
4.59
in
Speed Grade
OSKEW
-2
Table
STATPHAOFFSET
Table 38, page 20
610
400
Table 56, page 40
-1
in
45. Removed T
–0.28
Specifications. Updated
Table
1.33
5.22
in
Table
-1
Table 67
FS
Table
Table 52, page
and notes to
73.
Table
17. Removed V
14,
Table
670
440
-1L
–0.18
and T
1.79
5.63
through
-1L
Table
24. Updated
BUFHSKEW
and added
50,
including
OUTDUTY
Table 1
15, and
36.
Units
Units
ps
ps
ns
ns
ISE
56