XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 49

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Table 63: MMCM Specification (Cont’d)
Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in
Table 64: Global Clock Input to Output Delay Without MMCM
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Notes:
1.
T
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
T
MMCMCKO_PSDONE
ICKOF
When DIVCLK_DIVIDE = 3 or 4, F
This duty cycle specification does not apply to the GTH_QUAD (GTH) to MMCM connection. The GTH transceivers drive the MMCMs at the
following maximum frequencies: 323 MHz for -1 speed grade devices, 350 MHz for -2 speed grade devices, or 350 MHz for -3 speed grade
devices.
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Architecture Wizard.
Includes global clock buffer.
Calculated as F
When CASCADE4_OUT = TRUE, F
In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is
equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low
when the software can determine that the phase frequency detector input is less than 135 MHz.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Symbol
Table
Symbol
64. Values are expressed in nanoseconds unless otherwise noted.
VCO
Global Clock input and OUTFF without
MMCM
/128 assuming output duty cycle is 50%.
Phase Shift Clock-to-Out of PSDONE
Description
INMAX
OUTMIN
is 315 MHz.
is 0.036 MHz.
Description
www.xilinx.com
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
Device
0.32
4.91
4.89
5.02
5.02
5.30
5.40
5.18
5.20
5.38
N/A
N/A
N/A
N/A
-3
-3
0.34
Speed Grade
5.32
5.33
5.46
5.46
5.75
6.02
6.26
5.85
6.01
5.63
5.66
5.84
6.03
-2
Speed Grade
-2
0.38
5.88
6.00
6.13
6.13
6.43
6.72
6.97
6.54
6.71
6.30
6.34
6.53
6.71
-1
-1
0.38
-1L
6.02
6.13
6.27
6.27
6.37
6.60
6.87
6.49
6.61
N/A
N/A
N/A
N/A
-1L
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49