XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 36

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Input/Output Delay Switching Characteristics
Table 52: Input/Output Delay Switching Characteristics
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
IDELAYCTRL
T
F
IDELAYCTRL_REF_PRECISION
T
IODELAY
T
T
T
T
T
T
T
T
T
DLYCCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYRESOLUTION
IDELAYPAT_JIT
IODELAY_CLK_MAX
IODCCK_CE
IODCK_INC
IODCCK_RST
IODDO_T
IODDO_IDATAIN
IODDO_ODATAIN
Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
When HIGH_PERFORMANCE mode is set to TRUE
When HIGH_PERFORMANCE mode is set to FALSE.
Delay depends on IODELAY tap setting. See TRACE report for actual values.
/ T
Symbol
/ T
/ T
IODCKC_INC
IODCKC_CE
IODCKC_RST
Reset to Ready for IDELAYCTRL
REFCLK frequency = 200.0
REFCLK frequency = 300.0
REFCLK precision
Minimum Reset pulse width
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay
chain for clock pattern.
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23).
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23).
Maximum frequency of CLK input to
IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF
switching and through IODELAY
Propagation delay through IODELAY
Propagation delay through IODELAY
(3)
(4)
Description
(2)
www.xilinx.com
(1)
(1)
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
500.00
Note 5
Note 5
Note 5
50.00
–0.09
–0.02
–0.08
0.45/
0.23/
0.57/
3.00
±10
200
300
±5
±9
-3
0
420.00
Note 5
Note 5
Note 5
50.00
–0.09
–0.01
–0.08
0.53/
0.27/
0.62/
3.00
1/(32 x 2 x F
±10
200
300
±5
±9
-2
Speed Grade
0
300.00
Note 5
Note 5
Note 5
50.00
–0.09
–0.08
0.65/
0.31/
0.69/
3.00
REF
0.00
±10
200
±5
±9
-1
–
0
)
300.00
Note 5
Note 5
Note 5
52.50
–0.14
–0.04
–0.13
0.84/
0.27/
0.74/
3.25
±10
200
-1L
±5
±9
–
0
per tap
per tap
per tap
Units
MHz
MHz
MHz
MHz
µs
ns
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
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