LCMXO256C-3MN100I Lattice, LCMXO256C-3MN100I Datasheet - Page 15

• Manufacturer Part Number: LCMXO256C-3MN100I
• Description: IC PLD 256LUTS 78I/O 100CSBGA
• Manufacturer: Lattice

Specifications of LCMXO256C-3MN100I

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Package: 100CSBGA
• Family Name: MachXO
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 4.9 ns
• Number Of User I/os: 78
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Memory Type: SRAM
• Operating Temperature: -40 to 100 °C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1049

Lattice Semiconductor
The EBR memory supports three forms of write behavior for single or dual port operation:
1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current
2. Write Through – a copy of the input data appears at the output of the same port. This mode is supported for
3. Read-Before-Write – when new data is being written, the old contents of the address appears at the output.
FIFO Configuration
The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.
The range of programming values for these flags are in Table 2-7.
Table 2-7. Programmable FIFO Flag Ranges
The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset
state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in
the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the
FIFO.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-13.
address) does not appear on the output. This mode is supported for all data widths.
all data widths.
This mode is supported for x9, x18 and x36 data widths.
Full (FF)
Almost Full (AF)
Almost Empty (AE)
Empty (EF)
N = Address bit width
Flag Name
2-12
Programming Range
1 to (up to 2
1 to Full-1
1 to Full-1
0
N
MachXO Family Data Sheet
-1)
Architecture