STM32F217ZGT6 STMicroelectronics, STM32F217ZGT6 Datasheet - Page 102

• Manufacturer Part Number: STM32F217ZGT6
• Description: MCU ARM 1024KB FLASH 144LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F217ZGT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 132K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 24x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: STM32
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 120MHz
• Total Internal Ram Size: 132KB
• # I/os (max): 114
• Number Of Timers - General Purpose: 14
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Dac: 2(2-chx12-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11189

Electrical characteristics
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Figure 41. I
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
Figure 42. I
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
SD transmit
SD receive
byte.
byte.
WS output
SD transmit
SD receive
CPOL = 0
CPOL = 1
WS input
CPOL = 0
CPOL = 1
2
2
S slave timing diagram (Philips protocol)
S master timing diagram (Philips protocol)
t v(WS)
t su(WS)
t w(CKH)
t w(CKH)
LSB receive
Doc ID 17050 Rev 4
LSB transmit
LSB transmit
t su(SD_MR)
LSB receive
t su(SD_SR)
t c(CK)
(2)
t c(CK)
(2)
(2)
(2)
MSB receive
MSB transmit
MSB receive
DD
MSB transmit
t w(CKL)
and 0.7 × V
t w(CKL)
t f(CK)
(1)
t h(SD_MR)
DD
(1)
STM32F215xx, STM32F217xx
t v(SD_MT)
.
Bitn receive
t v(SD_ST)
t h(SD_SR)
Bitn transmit
Bitn transmit
Bitn receive
t r(CK)
LSB receive
t h(WS)
t h(SD_MT)
LSB transmit
t h(WS)
t h(SD_ST)
LSB transmit
LSB receive
ai14884b
ai14881b