STM32F217ZGT6 STMicroelectronics, STM32F217ZGT6 Datasheet - Page 29

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STM32F217ZGT6

Manufacturer Part Number
STM32F217ZGT6
Description
MCU ARM 1024KB FLASH 144LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheets

Specifications of STM32F217ZGT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
114
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
132K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 24x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Cpu Family
STM32
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
120MHz
Total Internal Ram Size
132KB
# I/os (max)
114
Number Of Timers - General Purpose
14
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Dac
2(2-chx12-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11189

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STM32F215xx, STM32F217xx
2.2.32
2.2.33
2.2.34
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared
with any other peripheral.
Universal serial bus on-the-go full-speed (OTG_FS)
The STM32F215xx and STM32F217xx embed an USB OTG full-speed device/host/OTG
peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the
USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable
endpoint setting and supports suspend/resume. The USB OTG full-speed controller
requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE
oscillator. The major features are:
Universal serial bus on-the-go high-speed (OTG_HS)
The STM32F215xx and STM32F217xx devices embed a USB OTG high-speed (up to
480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and
high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and
features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using
the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Internal FS OTG PHY support
External FS OTG PHY support through an I
Doc ID 17050 Rev 4
2
C connection
Description
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