ICS951402AGLF IDT, Integrated Device Technology Inc, ICS951402AGLF Datasheet

IC TIMING CTRL HUB P4 48-TSSOP

ICS951402AGLF

Manufacturer Part Number
ICS951402AGLF
Description
IC TIMING CTRL HUB P4 48-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS951402AGLF

Input
Crystal
Output
Clock
Frequency - Max
210MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
210MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
951402AGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS951402AGLFT
Manufacturer:
IDT/PBF
Quantity:
363
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Recommended Application:
ATI chipset, P4 system, Banias system
Output Features:
Features/Benefits:
Block Diagram
PD#/Vtt_PWRGD
0660—05/05/05
PCI66/33#SEL
CPU_STOP#
2 - Pairs of differential CPUCLKs (differential current mode)
1 - SDRAM @ 3.3V
8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running)
2 - AGP @ 3.3V
2- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
(Default is 24MHz)
3- REF @3.3V, 14.318MHz.
Support for Intel Banias power management features
Programmable output frequency, divider ratios, output rise/
falltime, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
operations.
Supports spread spectrum for EMI reduction; default is
spread spectrum ON.
PCI_STOP#
24_48SEL#
FS (4:0)
SDATA
SCLK
Integrated
Circuit
Systems, Inc.
PD#
X2
Programmable Timing Control Hub™ for P4™ processor
X1
2
C Index read/write and block read/write
XTAL
OSC
Spectrum
PLL2
Spread
Control
Config.
PLL1
Logic
Reg.
2
DIVDER
DIVDER
DIVDER
SDRAM
C
CPU
AGP
PCI
/ 2
Stop
Stop
2
2
6
2
3
1
2
SDRAM_OUT
48MHz (0:1)
24_48MHz
CPUCLKC (1:0)
PCICLK (5:0)
PCICLK_F (1:0)
AGP (1:0)
CPUCLKT (1:0)
REF (2:0)
I REF
*VttPWR_GD/PD# 10
** These inputs have a 120K pull down to GND.
FS3/PCICLK_F0 14
FS4/PCICLK_F1 15
PCI66/33#_SEL 11
* These inputs have a 120K pull up to VDD.
PCI_STOP#* 12
FS0/REF0 2
FS1/REF1 3
FS2/REF2 4
GNDREF 5
PCICLK0 16
PCICLK1 17
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
VDDREF 1
GNDPCI 18
GNDPCI 24
VDDPCI 13
VDDPCI 19
GND 8
Skew Requirements
VDD 9
48-Pin TSSOP & SSOP
PCI-PCI
AGP-AGP
CPU-AGP
CPU-PCI
AGP-PCI
AGP leading
CPU-SDRAM
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
X1 6
X2 7
Pin Configuration
Advance Information
48 VDDSDR
47 SDRAM_OUT
46 GNDSDR
45 CPU_STOP#*
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 GNDCPU
40 CPUCLKT0
39 CPUCLKC0
38 IREF
37 GND
36 AVDD
35 SCLK
34 SDATA
33 GNDAGP
32 AGPCLK0
31 AGPCLK1
30 VDDAGP
29 AVDD48
28 48MHz_0
27 48MHz_1
26 24_48MHz/SEL24_48#MHz**
25 GND48
<±350ps
<±350ps
<±500ps
<±500ps
<±1ns
<±1ns
ICS951402

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ICS951402AGLF Summary of contents

Page 1

Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ processor Recommended Application: ATI chipset, P4 system, Banias system Output Features: • Pairs of differential CPUCLKs (differential current mode) • SDRAM @ 3.3V • ...

Page 2

Integrated Circuit Systems, Inc. Pin Description PIN NUMBER PIN NAME 1 VDDREF 2 FS0/REF0 3 FS1/REF1 4 FS2/REF2 5 GNDREF GND 9 VDD 10 *VttPWR_GD/PD# 11 PCI66/33#_SEL 12 PCI_STOP#* 13 VDDPCI 14 FS3/PCICLK_F0 15 FS4/PCICLK_F1 ...

Page 3

Integrated Circuit Systems, Inc. Table 1: Clock Power Management Truth Table Byte 6 Byte 6 CPU_ PD# Bit 6 Bit 7 STOP ...

Page 4

Integrated Circuit Systems, Inc. 2 General I C serial interface information for the ICS951402 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) ...

Page 5

Integrated Circuit Systems, Inc. Serial Configuration Command Bitmap CPU MHz FS4 FS3 FS2 FS1 FS0 100. 133. 200. 166.65 0 ...

Page 6

Integrated Circuit Systems, Inc Table: Reserved Register Byte 0 Pin # Name - Reserved Bit 7 - Reserved Bit 6 Bit 5 - Reserved - Reserved Bit 4 Bit 3 - Reserved - Reserved Bit 2 - ...

Page 7

Integrated Circuit Systems, Inc Table: Reserved Register Byte 3 Pin # Name - Reserved Bit 7 - Reserved Bit 6 - Reserved Bit 5 - Reserved Bit 4 - Reserved Bit 3 Bit 2 - Reserved Bit ...

Page 8

Integrated Circuit Systems, Inc Table: Output Control Register Byte 6 Pin # Name - CPU_STOP# Bit 7 - PD# Bit 6 Bit 5 - PCI_F0 - PCI_F1 Bit 4 Bit 3 - CPUT/C_0 Bit 2 - CPUT/C_1 ...

Page 9

Integrated Circuit Systems, Inc Table: Watchdog Timer Register Byte 9 Pin # Name - WD7 Bit 7 Bit 6 - WD6 - WD5 Bit 5 Bit 4 - WD4 - WD3 Bit 3 Bit 2 - WD2 ...

Page 10

Integrated Circuit Systems, Inc Table: VCO Frequency Control Register Byte 12 Pin # Name - N Div7 Bit Div6 Bit Div5 Bit Div4 Bit Div3 ...

Page 11

Integrated Circuit Systems, Inc Table: Output Divider Control Register Byte 15 Pin # Name - SD Div3 Bit Div2 Bit 6 Bit Div1 Bit Div0 Bit 3 - ...

Page 12

Integrated Circuit Systems, Inc Table: Output Divider Control Register Byte 16 Pin # Name Bit 7 - AGP Div3 Bit 6 - AGP Div2 Bit 5 - AGP Div1 - AGP Div0 Bit 4 Bit 3 - ...

Page 13

Integrated Circuit Systems, Inc. Table 4:Skew Specification on Output Mode Bit3 Bit2 Table: Group Skew Control Register Byte 19 Pin # Name - Reserved Bit 7 - Reserved Bit ...

Page 14

Integrated Circuit Systems, Inc Table: Slew Rate Control Register Byte 21 Pin # Name Bit 7 - 24_48Slw1 - 24_48Slw0 Bit 6 Bit 5 - AGPSlw1 - AGPSlw0 Bit 4 Bit 3 - Reserved - Reserved Bit ...

Page 15

Integrated Circuit Systems, Inc Table: Reserved Control Register Byte 24 Pin # Name - Reserved Bit 7 - Reserved Bit 6 - Reserved Bit 5 - Reserved Bit 4 - Reserved Bit 3 - Reserved Bit 2 ...

Page 16

Integrated Circuit Systems, Inc. Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . ...

Page 17

Integrated Circuit Systems, Inc. Electrical Characteristics - CPU (0.7V Select 70C; VDD=3.3V +/-5 PARAMETER SYMBOL Current Source Output Impedance Output High Voltage Output Low Voltage Voltage High VHigh Voltage Low Max Voltage Min Voltage ...

Page 18

Integrated Circuit Systems, Inc. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB 70C; VDD=3.3V +/-5 PARAMETER SYMBOL Output Frequency Output Impedance R Output High Voltage V Output Low Voltage V Output High Current Output ...

Page 19

Integrated Circuit Systems, Inc. Electrical Characteristics - REF 70C; VDD=3.3V +/-5 PARAMETER SYMBOL Output Frequency Output Impedance R Output High Voltage V Output Low Voltage V Output High Current Output Low Current Rise Time ...

Page 20

Integrated Circuit Systems, Inc. Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 21

Integrated Circuit Systems, Inc. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low ...

Page 22

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA Ordering Information ICS951402yGLF-T Example: ICS XXXX y G LF- T 0660—05/05/05 c SYMBOL ...

Page 23

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 45° .10 (.004) C .10 (.004) C Ordering Information ICS951402yFLF-T Example: ICS XXXX y F LF- T Designation for tape ...

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