ICS951402AGLF IDT, Integrated Device Technology Inc, ICS951402AGLF Datasheet - Page 2

• Manufacturer Part Number: ICS951402AGLF
• Description: IC TIMING CTRL HUB P4 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS951402AGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 210MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 210MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951402AGLF

Pin Description
0660—05/05/05
PIN NUMBER
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
Integrated
Circuit
Systems, Inc.
24_48MHz/SEL24_48#MHz**
*VttPWR_GD/PD#
FS3/PCICLK_F0
FS4/PCICLK_F1
PCI66/33#_SEL
CPU_STOP#*
SDRAM_OUT
PCI_STOP#*
CPUCLKC0
CPUCLKC1
CPUCLKT0
CPUCLKT1
PIN NAME
FS0/REF0
FS1/REF1
FS2/REF2
AGPCLK1
AGPCLK0
48MHz_1
48MHz_0
GNDAGP
GNDCPU
VDDCPU
GNDSDR
VDDSDR
VDDREF
GNDREF
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDAGP
AVDD48
VDDPCI
GNDPCI
VDDPCI
GNDPCI
GND48
SDATA
AVDD
SCLK
GND
VDD
GND
IREF
X1
X2
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
IN
IN
IN
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active high input. / Asynchronous active low input pin used to power
down the device into a low power state.
Selects all PCI clock frequencies to be 33Mhz or 66Mhz. 0 = 33Mhz , 1
= 66Mhz
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Ground pin for the 48MHz outputs
24/48MHz clock output / Latched select input for 24/48MHz output.
0=48MHz, 1 = 24MHz.
48MHz clock output.
48MHz clock output.
Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
Power supply for AGP clocks, nominal 3.3V
AGP clock output
AGP clock output
Ground pin for the AGP outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
3.3V Analog Power pin for Core PLL
Ground pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
Ground pin for the CPU outputs
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
Stops all CPUCLK besides the free running clocks
Ground pin for the SDRAM outputs.
SDRAM seed clock output for external buffer
Supply for SDRAM clocks, nominal 3.3V.
2
DESCRIPTION
Advance Information
ICS951402