ICS951402AGLF IDT, Integrated Device Technology Inc, ICS951402AGLF Datasheet - Page 21

• Manufacturer Part Number: ICS951402AGLF
• Description: IC TIMING CTRL HUB P4 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS951402AGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 210MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 210MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951402AGLF

PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
0660—05/05/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Integrated
Circuit
Systems, Inc.
PCI_F 33MHz
PCI_STOP#
CPU_STOP#
PCI 33MHz
CPUC
CPUT
tsu
Assertion of CPU_STOP# Waveforms
Assertion of PCI_STOP# Waveforms
21
2
C configuration to be stoppable via
Advance Information
ICS951402