SI5017-D-GM Silicon Laboratories Inc, SI5017-D-GM Datasheet - Page 19

• Manufacturer Part Number: SI5017-D-GM
• Description: IC CLOCK/DATA RECOVERY 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5017-D-GM

• Input: Differential
• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1279

5. Pin Descriptions: Si5017
1,2,11,14,18,
21,25
Pin #
3
4
5
6
SLICE_LVL
Pin Name
REFCLK+
REFCLK–
LOS_LVL
VDD
Figure 15. Si5017 Pin Configuration
SLICE_LVL
I/O
Table 8. Si5017 Pin Descriptions
REFCLK+
REFCLK–
LOS_LVL
I
I
I
VDD
VDD
LOL
1
2
3
4
5
6
7
Signal Level
See Table 2
28 27 26 25 24 23 22
8
3.3 V
9
Rev. 1.5
10 11 12 13 14
GND
Pad
Supply Voltage.
Nominally 3.3 V.
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 13 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 7 on page 13 for typical reference clock
frequencies.
21
20
19
18
17
16
15 TDI
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
Description
Si5017
19