SI5017-D-GM Silicon Laboratories Inc, SI5017-D-GM Datasheet - Page 24

• Manufacturer Part Number: SI5017-D-GM
• Description: IC CLOCK/DATA RECOVERY 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5017-D-GM

• Input: Differential
• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1279

Si5017
D
Revision 0.1 to Revision 1.0
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Revision 1.0 to Revision 1.1
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Revision 1.1 to Revision 1.2
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24
OCUMENT
Added Figure 4, “PLL Acquisition Time,” on page 6.
Table 2 on page 7
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Table 3 on page 8
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Table 4 on page 9
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Removed “Hysteresis Dependency” Figure.
Added Figure 7, “LOS Signal Hysteresis,” on page
13.
Corrected error: Table 8 on page 19—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
Corrected “Revision 0.1 to Revision 1.0” Change
List.
Added Figure 5, “LOS Response Time,” on page 6.
Updated Table 2 on page 7
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Table 3 on page 8.
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Updated Table 8 on page 19
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(REFCLK)
(reference clock applied)
(reference-less operation)
goes out of Lock
goes into Lock
updated values.
Added “Output Common Mode Voltage (CLKOUT)” with
updated values.
Added FEC (2.7 GHz) Supply Current
Updated values: Supply Current
Added FEC (2.7 GHz) Power Dissipation
Updated values: Power Dissipation
Updated values: Common Mode Input Voltage
Updated values: Output Common Mode Voltage
Added separate Output Clock Rise Time
Added separate Output Clock Fall Time
Updated values: Output Clock Rise Time
Updated values: Output Clock Fall Time
Updated values: Jitter Tolerance (OC-48) for f = 1 MHz
Updated values: Acquisition Time
Updated values: Acquisition Time
Updated values: Freq Difference at which Receive PLL
Updated values: Freq Difference at which Receive PLL
Added “Output Common Mode Voltage (DOUT)” with
Added “Output Clock Duty Cycle”
Added “Loss-of-Signal Response Time”
Changed “clock input” to “DIN inputs” for Loss-of-Signal.
C
HANGE
L
IST
Rev. 1.5
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Revision 1.2 to Revision 1.3
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Revision 1.3 to Revision 1.4
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Revision 1.4 to Revision 1.5
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Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
Updated Table 9, “Package Diagram Dimensions,”
on page 23.
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Table 2 on page 7.
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Table 3 on page 8.
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Table 4 on page 9.
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Updated "6. Ordering Guide" on page 22.
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Updated Table 2 on page 7.
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Updated Table 3 on page 8.
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Updated Table 4 on page 9.
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Updated "4.7. Loss-of-Signal (LOS)" on page 13.
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Updated "4.9. Data Slicing Level" on page 14.
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Added "7. Top Mark" on page 22.
Updated "8. Package Outline" on page 23.
Changed dimension A.
Changed dimension E2.
Updated power consumption.
Updated R
Updated clock to data delay.
Updated slicing level accuracy.
Updated tolerance.
Updated acquisition time.
Updated reference clock information.
Added “X” to part number.
Added limits for V
Updated V
Updated T
Updated T
Revised SLICE specification.
T
Added note describing valid signal.
Updated Figure 6, “LOS_LVL Mapping,” on page 13.
Added Figure 8 on page 14.
Revised text.
AQ
min/max values updated.
OD
Cr-D
Cf-D
IN
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ICM
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