LMK04001BISQE/NOPB National Semiconductor, LMK04001BISQE/NOPB Datasheet - Page 5

• Manufacturer Part Number: LMK04001BISQE/NOPB
• Description: IC CLOCK COND 1.5GHZ W/PLL 48LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock Conditionerr

Specifications of LMK04001BISQE/NOPB

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS, 2VPECL, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.57GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 1.57GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK04001BISQETR

17.0 Application Information ................................................................................................................. 39
18.0 Physical Dimensions .................................................................................................................... 53
19.0 Ordering Information .................................................................................................................... 53
16.10 REGISTER 13 .................................................................................................................... 36
16.11 REGISTER 14 .................................................................................................................... 37
16.12 REGISTER 15 .................................................................................................................... 38
17.1 SYSTEM LEVEL DIAGRAM ................................................................................................... 39
17.2 LDO BYPASS AND BIAS PIN ................................................................................................ 40
17.3 LOOP FILTER ..................................................................................................................... 40
17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS ..................................... 43
17.5 POWER SUPPLY CONDITIONING ........................................................................................ 43
17.6 THERMAL MANAGEMENT ................................................................................................... 43
17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) ................................. 44
17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) ..................................................... 47
17.9 DRIVING CLKin AND OSCin INPUTS ..................................................................................... 49
17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE .............................................. 49
17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE .......................... 49
16.9.1 PLL1_N: PLL1_N Counter ........................................................................................... 35
16.9.2 PLL1_R: PLL1_R Counter ........................................................................................... 36
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control
16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable ......................................................... 36
16.10.2 EN_Fout: Fout Power Down Bit .................................................................................. 36
16.10.3 CLK Global Enable: Clock Global enable bit ................................................................. 36
16.10.4 POWERDOWN Bit -- Device Power Down .................................................................... 36
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit .................................................. 36
16.10.6 PLL2 Internal Loop Filter Component Values ................................................................ 36
16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE ............................................................ 37
16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register ............................................... 37
16.11.2 PLL2_R: PLL2_R Counter .......................................................................................... 37
16.11.3 PLL_MUX: LD Pin Selectable Output ........................................................................... 37
16.12.1 PLL2_N: PLL2_N Counter .......................................................................................... 38
16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control ................................... 38
16.12.3 VCO_DIV: PLL2 VCO Divide Register ......................................................................... 38
17.8.1 Termination for DC Coupled Differential Operation .......................................................... 47
17.8.2 Termination for AC Coupled Differential Operation .......................................................... 47
17.8.3 Termination for Single-Ended Operation ........................................................................ 48
17.9.1 Driving CLKin Pins with a Differential Source .................................................................. 49
17.9.2 Driving CLKin Pins with a Single-Ended Source .............................................................. 49
(PLL1_CP_POL) ................................................................................................................ 36
5
www.national.com