IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 15
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IDT82V3280PFG
Manufacturer Part Number
IDT82V3280PFG
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280PFG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3280PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V3280PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Table 1: Pin Description (Continued)
Pin Description
IDT82V3280
MPU_MODE0
MPU_MODE1
MPU_MODE2
OUT6_POS
OUT6_NEG
OUT7_POS
OUT7_NEG
OUT8_POS
OUT8_NEG
INT_REQ
Name
OUT4
OUT5
OUT9
CS
Pin No.
93
94
34
35
36
37
28
27
95
70
60
59
58
8
pull-down
pull-up
I/O
O
O
O
O
O
O
O
I
I
PECL/LVDS
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
AMI
Microprocessor Interface
OUT4: Output Clock 4
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT5: Output Clock 5
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
OUT9: Output Clock 9
A 1.544 MHz (SONET) / 2.048 MHz (SDH) BITS/SSU clock is output on this pin.
CS: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
MPU_MODE[2:0]: Microprocessor Interface Mode Selection
The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motor-
ola and Serial.
During reset, these pins determine the default value of the MPU_SEL_CNFG[2:0] bits (b2~0,
7FH) as follows:
001 (EPROM mode);
010 (Multiplexed mode);
011 (Intel mode);
100 (Motorola mode);
101 (Serial mode);
110 - 111 (Reserved).
After reset, these pins are general purpose inputs. The microprocessor interface mode is
selected by the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH).
The value of these pins is always reflected by the MPU_PIN_STS[2:0] bits (b2~0, 02H).
15
Description
4
4
4
4
, N x T1
, N x T1
, N x T1
, N x T1
1
5
5
5
5
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
December 9, 2008
6
6
6
6
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
WAN PLL
7
7
7
7
,
,
,
,