IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 71

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control
Programming Information
IDT82V3280
Address: 0BH
Type: Read / Write
Default Value: 100X01X1
FREQ_MON_C
Bit
7
6
5
4
3
2
1
0
LK
7
FREQ_MON_HARD_EN
LOS_FLAG_TO_TDO
FREQ_MON_CLK
ULTR_FAST_SW
PBO_FREZ
EXT_SW
PBO_EN
LOS_FLAG_TO
Name
-
_TDO
6
The bit selects a reference clock for input clock frequency monitoring.
0: The output of T0 DPLL.
1: The master clock. (default)
The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin.
0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default)
1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE
1149.1.
This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more.
0: Valid. (default)
1: Invalid.
This bit determines the T0 input clock selection.
0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H).
1: External Fast selection.
The default value of this bit is determined by the FF_SRCSW pin during reset.
This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the cur-
rent phase offset when a PBO event is triggered.
0: Not frozen. (default)
1: Frozen. Further PBO events are ignored and the current phase offset is maintained.
This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover
mode or Free-Run mode occurs.
0: Disabled.
1: Enabled. (default)
Reserved.
This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the
reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the mas-
ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH).
0: Disabled.
1: Enabled. (default)
ULTR_FAST_SW
5
EXT_SW
4
71
PBO_FREZ
3
Description
PBO_EN
2
1
-
December 9, 2008
FREQ_MON_H
ARD_EN
0
WAN PLL