IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 44

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

3.14
device.
configured as the Slave. The configuration is made by the MS/SL pin
and the MS_SL_CTRL bit (b0, 13H), as shown in
Table 29: Device Master / Slave Control
Functional Description
IDT82V3280
Master / Slave configuration is only supported by the T0 path of the
Two devices should be used together in order to:
Of the two devices, one is configured as the Master and the other is
• Enable system protection against single chip failure;
• Guarantee no service interrupt during system maintenance, such
MS/SL pin
as software or hardware upgrade.
High
Low
Master / Slave Control
MASTER / SLAVE CONFIGURATION
Hardware
Backplane
control
MS_SL_CTRL Bit
0
1
0
1
Figure 13. Physical Connection Between Two Devices
Table
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Result
Master
Master
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29:
Slave
Slave
EX_SYNC1
EX_SYNC1
IN10
IN11
IN12
IN14
MS/SL
IN1
IN1
IN10
IN11
IN12
MS/SL
IN14
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Chip A
Chip B
MFRSYNC_2K
MFRSYNC_2K
FRSYNC_8K/
FRSYNC_8K/
44
input clock and the frame sync output signals from the two devices are
at the same frequency offset and phase. Refer to
SYNC Output Signals
the IN11 should not be selected by the T0 DPLL; in the Slave, the follow-
ing functions are automatically forced:
tions can still be configured, but their configuration does not take any
effect. The frequency of the T0 selected input clock IN11 is recom-
mended to be 6.48 MHz.
OUT1
OUT2
OUT7
OUT2
OUT1
OUT7
In this application, all the output clocks derived from the T0 selected
The difference between the Master and the Slave is: in the Master,
In the Slave, the corresponding registers of the above forced func-
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• The T0 selected input clock is IN11;
• T0 PBO is disabled;
• T0 DPLL operates at the acquisition bandwidth and damping fac-
• EX_SYNC1 is used for synchronization;
• T0 DPLL operates in Locked mode.
one output
frame sync
frame sync
tor;
one output
one output
one output
clock
signal
signal
clock
for details.
Backplane connections
Backplane
Chapter 3.13.2 Frame
December 9, 2008
WAN PLL