IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 76

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

INTERRUPTS3_STS - Interrupt Status 3
Programming Information
IDT82V3280
Address: 0FH
Type: Read / Write
Default Value: 11X10000
EX_SYNC_ALARM
Bit
7
6
5
4
3
2
1
0
7
EX_SYNC_ALARM
INPUT_TO_T4
AMI2_VIOL
AMI1_VIOL
AMI2_LOS
AMI1_LOS
T4_STS
Name
-
T4_STS
6
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H).
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates whether all the input clocks for T4 path changes to be unqualified; i.e., whether the
HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
This bit indicates whether IN2 has an AMI violation.
0: Has no AMI violation. (default)
1: Has an AMI violation.
This bit is cleared by writing a ‘1’.
This bit indicates whether IN2 has a LOS error.
0: Has no LOS error. (default)
1: Has a LOS error.
This bit is cleared by writing a ‘1’.
This bit indicates whether IN1 has an AMI violation.
0: Has no AMI violation. (default)
1: Has an AMI violation.
This bit is cleared by writing a ‘1’.
This bit indicates whether IN1 has a LOS error.
0: Has no LOS error. (default)
1: Has a LOS error.
This bit is cleared by writing a ‘1’.
5
-
INPUT_TO_T4
4
76
AMI2_VIOL
3
Description
AMI2_LOS
2
AMI1_VIOL
1
December 9, 2008
AMI1_LOS
0
WAN PLL