MPC972FA Freescale Semiconductor, MPC972FA Datasheet - Page 10

• Manufacturer Part Number: MPC972FA
• Description: IC PLL CLOCK DRIVER 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MPC972FA

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC972. From the data sheet the I
sourced through the V
maximum), assuming that a minimum of 2.935 V must be
maintained on the V
tolerated when a 3.3 V V
in Figure 10 must have a resistance of 5–10 Ω to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for noise
whose spectral content is above 20 KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the bandwidth
of the PLL.
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
Driving Transmission Lines
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of approximately 10 Ω the drivers can
drive either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
level of DC current and thus only a single terminated line can
be driven by each output of the MPC972 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 11 illustrates an output driving a single series terminated
line vs two series terminated lines in parallel. When taken to its
extreme the fanout of the MPC972 clock driver is effectively
doubled due to its capability to drive multiple lines.
MPC972
Although the MPC972 has several design features to
The MPC972 clock driver was designed to drive high speed
In most high performance clock networks point–to–point
10
CCA
CC
CCA
/2. This technique draws a fairly high
CC
pin very little DC voltage drop can be
supply is used. The resistor shown
pin) is typically 15 mA (20 mA
VCCA
current (the current
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC972 output buffers is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output–to–output skew of the
MPC972. The output waveform in Figure 12 shows a step in the
waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
43 Ω series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
reflection coefficient, to 2.8 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0 ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 13 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
The waveform plots of Figure 12 show the simulation results
At the load end the voltage will double, due to the near unity
Since this step is well above the threshold region it will not
Figure 11. Single versus Dual Transmission Lines
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40 V
Ω
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MOTOROLA