MPC972FA Freescale Semiconductor, MPC972FA Datasheet - Page 6

• Manufacturer Part Number: MPC972FA
• Description: IC PLL CLOCK DRIVER 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MPC972FA

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6. 50Ω transmission line terminated into V
7. t
Programming the MPC972
programming devices in the Motorola timing solution portfolio.
With three independent banks of four outputs as well as an
independent PLL feedback output the total number of possible
configurations is too numerous to tabulate. Table 1 tabulates
the various selection possibilities for the three banks of outputs.
The divide numbers presented in the table represent the divider
applied to the output of the VCO for that bank of outputs. To
determine the relationship between the three banks the three
divide ratios would be compared. For instance if a frequency
relationship of 5:3:2 was desired the following selection could
be made. The Qb outputs could be set to ÷10, the Qa outputs
to ÷6 and the Qc outputs to ÷4. With this output divide selection
the desired 5:3:2 relationship would be generated. For
situations where the VCO will run at relatively low frequencies
the PLL may not be stable for the desired divide ratios. For
these circumstances the VCO_Sel pin allows for an extra ÷2 to
be added into the clock path. When asserted this pin will
maintain the desired output relationships, but will provide an
enhanced lock range for the PLL. Once the output frequency
relationship is set and the VCO is in its stable range the
feedback output would be programmed to match the input
reference frequency.
separate feedback output is provided to optimize the flexibility
of the device. If in the example above the input reference
AC CHARACTERISTICS (T
MPC972
t
t
t
t
f
f
t
t
t
t
f
The MPC972 is one of the most flexible frequency
The MPC972 offers only an external feedback to the PLL. A
r
pw
pd
os
VCO
max
jitter
PLZ
PZL
lock
MAX
6
, t
periods. The t
pd
Symbol
f
, t
, t
is specified for a 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference
PHZ
PZH
pd
Output Rise/Fall Time
Output Duty Cycle
SYNC to Feedback
Propagation Delay
Output-to-Output Skew
VCO Lock Range
Maximum Output Frequency
Cycle–to–Cycle Jitter (Peak–to–Peak)
Output Disable Time
Output ENable TIme
Maximum PLL Lock Time
Maximum Frz_Clk Frequency
does not include jitter.
A
= 0° to 70°C; V
Characteristic
CC
/2.
CC
APPLICATIONS INFORMATION
= 3.3V ±5%)
TCLK0
TCLK1
Q (÷2)
Q (÷4)
Q (÷6)
Q (÷8)
t
CYCLE
–750
–270
–330
0.15
Min
200
2
2
frequency was equal to the lowest output frequency the
feedback output would be set in the ÷10 mode. If the input
needed to be half the lowest frequency output the fselFB2 input
could be asserted to halve the feedback frequency. This action
multiplies the output frequencies by two relative to the input
reference frequency. With 7 unique feedback divide capabilities
there is a tremendous amount of flexibility. Again assume the
above 5:3:2 relationship is needed with the highest frequency
output equal to 100 MHz. If one was also constrained because
the only reference frequency available was 50 MHz the setup
in Figure 6 could be used. The MPC972 provides the 100, 66
and 40 MHz outputs all synthesized from the 50 MHz source.
With its multitude of divide ratio capabilities the MPC972 can
generate almost any frequency from a standard, common
frequency already present in a design. Figure 7 and Figure 8
illustrate a few more examples of possible MPC972
configurations.
its arsenal. The Inv_Clk input pin when asserted will invert the
Qc2 and Qc3 outputs. This inversion will not affect the
output–output skew of the device. This inversion allows for the
development of 180° phase shifted clocks. This output could
also be used as a feedback output to the MPC972 or a second
PLL device to generate early or late clocks for a specific design.
Figure 9 illustrates the use of two MPC972’s to generate two
banks of clocks with one bank divided by 2 and delayed by 180°
relative to the first.
/2
The MPC972 has one more programming feature added to
t
CYCLE
±500
±100
Typ
130
70
/2
t
CYCLE
+750
Max
530
470
550
480
125
120
1.2
80
60
10
10
20
8
/2
MHz
MHz
MHz
Unit
ms
ns
ps
ps
ps
ps
ns
ns
0.8 to 2.0V, Note 6.
Note 6.
Notes 6., 7.; QFB = ÷8
Note 6.
Note 6.
Note 6.
Note 6.
Note 6.
Condition
MOTOROLA