ISL12032IVZ-T Intersil, ISL12032IVZ-T Datasheet - Page 10

• Manufacturer Part Number: ISL12032IVZ-T
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ-T

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12032IVZ-TTR

Brownout Detection
The ISL12032 monitors the V
provides a warning if the V
levels. There are six levels that can be selected for the trip
level. These values are 85% below popular V
LVDD bit in the SRDC register will be set to “1” when
Brownout is detected. Note that the I
active until the Battery V
Battery Level Monitor
The ISL12032 has a built in warning feature once the VBAT
battery level drops first to 85% and then to 75% of the
battery’s nominal VBAT level. When the battery voltage falls
to between 85% and 75%, the LBAT85 bit is set in the SRDC
register. When the level drops below 75%, both LBAT85 and
LBAT75 bits are set in the SRDC register. The trip levels for
the 85% and 75% levels are set using the PWRBAT register.
The Battery Timestamp Function permits recovering the
time/date when V
low enough to enable switchover to the battery, the RTC
time/date are written into the TSV2B section. If there are
multiple power-down cycles before reading these registers,
the first values stored in these registers will be retained and
ensuing events will be ignored. These registers will hold the
original power-down value until they are cleared by writing
“00h” to each register or setting the CLRTS bit to “1”.
The V
time/date when V
high enough to enable switchover to V
are written into the TSB2V register. If there are multiple
power-down cycles before reading these registers, the most
recent event is retained in these registers and the previous
events will be ignored. These registers will hold the original
power-down value until they are cleared by writing “00h” to
each register.
Real Time Clock Operation
The Real Time Clock (RTC) maintains an accurate internal
representation of tenths of a second, second, minute, hour,
day of week, date, month, and year. The RTC also has leap-
year correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24 hour or
AM/PM format. When the ISL12032 powers up after the loss
of both V
until at least one byte is written to the clock register.
Alarm Operation
The alarm mode is enabled via the MSB bit. Single event or
interrupt alarm mode is selected via the IM bit. The standard
alarm allows for alarms of time, date, day of the week,
month, and year. When a time alarm occurs in single event
mode, the IRQ pin will be pulled low and the corresponding
alarm status bit (ALM0 or ALM1) will be set to “1”. The
status bits can be written with a “0” to clear, or if the ARST
DD
DD
Timestamp Function permits recovering the
and VBAT, the clock will not begin incrementing
DD
DD
power loss occurred. Once the V
recovery occurred. Once the V
TRIP
DD
10
DD
level is reached.
level drops below prescribed
level continuously and
2
C serial bus remains
DD
, the RTC time/date
DD
levels. The
DD
DD
is
is
ISL12032
bit is set, a single read of the SRDC status register will
clear them.
The pulsed interrupt mode (setting the IM bit to “1”) activates
a repetitive or recurring alarm. Hence, once the alarm is set,
the device will continue to output a pulse for each occurring
match of the alarm and present time. The Alarm pulse will
occur as often as every minute (if only the nth second is set)
or as infrequently as once a year (if at least the nth month is
set). During pulsed interrupt mode, the IRQ pin will be pulled
LOW for 250ms and the alarm status bit (ALM0 or ALM1) will
be set to “1”.
The alarm function is not available during battery backup
mode.
Frequency Output Mode
The ISL12032 has the option to provide a clock output signal
using the F
mode is set by using the FO bits to select 7 possible output
frequency values from 1.0Hz to 32.768kHz, and disable. The
frequency output can be enabled/disabled during battery
backup mode by setting the FOBATB bit to “0”. When the AC
input is qualified (within the parameters of AC qualification)
then the Frequency Output for values 50/60Hz and below
are derived from the AC input clock. Higher frequency F
values are derived from the crystal. If the AC clock input is
not qualified, then all F
crystal.
General Purpose User SRAM
The ISL12032 provides 128 bytes of user SRAM. The SRAM
will continue to operate in battery backup mode. However, it
should be noted that the I
backup mode unless enabled by the I
I
The ISL12032 has an I
access to the control and status registers and the user
SRAM. The I
industry I
signal (SDA) and a clock signal (SCL).
The I
set in the PWRVDD register. It can also operate in battery
backup mode by setting the I2CBAT bit to “1”, in which case
operation will be down to VBAT = 1.8V.
Register Descriptions
The battery-backed registers are accessible following an I
slave byte of “1101 111x” and reads or writes to addresses
[00h:47h]. The defined addresses and default values are
described in the Table 1. The battery backed general
purpose SRAM has a different slave address (1010 111x), so
it is not possible to read/write that section of memory while
accessing the registers.
2
C Serial Interface
2
C bus normally operates down to the V
2
C serial bus protocols using a bi-directional data
OUT
2
C serial interface is compatible with other
CMOS output pin. The frequency output
OUT
2
C serial bus interface that provides
2
C bus is disabled in battery
values are derived from the
2
CBAT bit.
DD
trip point
April 16, 2009
FN6618.2
OUT
2
C