ISL12032IVZ-T Intersil, ISL12032IVZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL12032IVZ-T
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ-T

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12032IVZ-TTR

DstHrFd controls the hour that DST begins. It includes the
MIL bit, which is in the corresponding RTC register. The RTC
hour and DstHrFd registers need to match formats (Military
or AM/PM) in order for the DST function to work. The default
value for DST hour is 2:00AM (02h). The time is advanced
from 2:00:00AM to 3:00:00AM for this setting.
DST REVERSE REGISTERS (19H TO 1CH)
DST end (reverse) is controlled by the following DST
Registers.
DstMoRv sets the Month that DST ends. The default value
for the DST end month is October (10h).
DstDwRv controls the Day of the Week that DST should end.
The DwRvE bit sets the priority of the Day of the Week over
ALARM Registers (1Dh to 28h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
Single Event Mode is enabled by setting either ALE0 or
ALE1 to 1, then setting bit 7 on any of the Alarm registers
(ESCA... EDWA) to “1”, and setting the IM bit to “0”. This
mode permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM bit
is set to “1” and the IRQ output will be pulled LOW and will
remain LOW until the ALM bit is reset. This can be done
ADDRESS
ADDRESS
1Ah
1Bh
1Ch
15h
16h
17h
18h
19h
Month Forward
Month Reverse
Hour Forward
Date Forward
Hour Reverse
Date Reverse
Day Forward
Day Reverse
FUNCTION
NAME
20
HrFdMIL
HrRvMIL
DSTE
7
0
0
7
0
0
0
DwFdE
DwRvE
6
0
0
6
0
0
0
0
TABLE 26. DST FORWARD REGISTERS
TABLE 27. DST REVERSE REGISTERS
WkRv12
WkFd12
HrFd21
DtRv21
HrRv21
DtFd21
5
0
5
0
ISL12032
MoRv20
WkRv11
MoFd20
WkFd11
DtRv20
HrRv20
HrFd20
DtFd20
the Date. For DwRvE = 1, Day of the week is the priority. Note
that Day of the week counts from 0 to 6, like the RTC
registers. The default for DST DwRv end is Sunday (00h).
DstDtRv controls which Date DST ends. The default value
for DST Date Reverse is on the first date of the month. The
DstDtRv is only effective if the DwRvE = 0.
DstHrRv controls the hour that DST ends. It includes the MIL
bit, which is in the corresponding RTC register. The RTC
hour and DstHrRv registers need to match formats (Military
or AM/PM) in order for the DST function to work. The default
value sets the DST end at 2:00AM. The time is set back from
2:00:00AM to 1:00:00AM for this setting.
manually or by using the auto-reset feature. Since the IRQ
output is shared by both alarms, they both need to be reset
in order for the IRQ output to go HIGH.
Interrupt Mode is enabled by setting either ALE0 or ALE1 to
1, then setting bit 7 on any of the Alarm registers (ESCA...
EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit
to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ
output will now be pulsed each time an alarm occurs (either
AL0 or AL1). This means that once the interrupt mode alarm
is set, it will continue to alarm until it is reset.
To clear a single event alarm, the corresponding ALM0 or
ALM1 bit in the SRDC register must be set to “0” with a write.
Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the
ALM0 and ALM1 bits will automatically be cleared when the
status register is read.
The IRQ output will be set by an alarm match for either
ALM0 or ALM1.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
4
4
MoRv13
WkRv10
WkFd10
MoFd13
HrRv13
DtRv13
DtFd13
HrFd13
3
3
MoRv12
DwRv12
MoFd12
DwFd12
DtRv12
HrRv12
DtFd12
HrFd12
2
2
MoRv11
DwRv11
DwFd11
MoFd11
DtRv11
HrRv11
DtFd11
HrFd11
1
1
MoRv10
DwRv10
DwFd10
HrRv10
MoFd10
DtRv10
DtFd10
HrFd10
April 16, 2009
0
0
FN6618.2